Live Demonstration for Input-Sparsity-Aware RRAM Processing-in-Memory Chip. - Junjie Wang 008; Shuang Liu 007; Ruicheng Pan; Shiqin Yan; Yihe Liu; Yang Liu 062 (ISCAS, 2024)

Design and implementation of a charge-sharing in-memory-computing macro with sparse feature for quantized neural network. - Yihe Liu; Junjie Wang 008; Shuang Liu 007; Mingyuan Sun; Xiaoyang Zhang; Jingtao Zhou; Shiqin Yan; Ruicheng Pan; Hao Hu; Yang Liu 062 (Microelectron. J., 2024)