A 0.6-V 9.38-Bit 6.9-kS/s Capacitor-Splitting Bypass Window SAR ADC for Wearable 12-Lead ECG Acquisition Systems. - Kangkang Sun; Jingjing Liu 005; Feng Yan; Yuan Ren; Ruihuang Wu; Bingjun Xiong; Zhipeng Li; Jian Guan (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A Sub-0.9-ps Static Phase Offset 500 MHz Delay-Locked Loop With a Large Gain Phase Detector. - Jingjing Liu 005; Ruihuang Wu; Haoning Sun; Bingjun Xiong; Feng Yan; Kangkang Sun; Zhipeng Li; Jian Guan (IEEE Trans. Very Large Scale Integr. Syst., 2025)