A 68.5 dB-SNDR, 12.4-fJ/conv.-step, 100-MS/s pipelined-SAR ADC with PVT-enhanced circuitry. - Haolin Han; Ruili Ren; Yi Shen 007; Ruixue Ding; Shubin Liu; Hongzhi Liang (Microelectron. J., 2024)

A PVT-robust Gm-R-based residue amplifier with folded positive feedback technique. - Haolin Han; Jinwei Zhang; Ruili Ren; Yi Shen 007; Shubin Liu; Ruixue Ding (Microelectron. J., 2024)

A Power-Efficient Clock Circuit and Output Serializing Technique Integrated in a 12-bit 10-GS/s ADC. - Haolin Han; Shubin Liu; Hongzhi Liang; Yi Shen 007; Jianyu Guo; Ruili Ren; Zhangming Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)