Low-power motion-estimation architecture based on a novel early-jump-out technique. - Wujian Zhang; Runde Zhou; Toshio Kondo (ISCAS (5), 2001)

Single-track asynchronous pipeline controller design. - Yong Xiao; Runde Zhou (ASP-DAC, 2005)

A Novel Scheme of Implementing High-Speed High-Probability-Resolution Digital AWGN Generators. - Jianliang Zhang; Sheng Zhang 003; Shuo Wang; Runde Zhou (J. Circuits Syst. Comput., 2007)

Embedded high-speed BCH decoder for new-generation NOR flash memories. - Xueqiang Wang; Dong Wu; Chaohong Hu; Liyang Pan; Runde Zhou (CICC, 2009)

Low Power Inductor-less Pulse UWB Transceiver. - Mengmeng Liu; Sheng Zhang 003; Shuo Wang; Jianliang Zhang; Runde Zhou (ISCAS, 2009)

Low Clock-Swing TSPC Flip-Flops for Low-Power Applications. - Yingbo Hu; Runde Zhou (J. Circuits Syst. Comput., 2009)

A High-Speed Two-Cell BCH Decoder for Error Correcting in MLC nor Flash Memories. - Xueqiang Wang; Liyang Pan; Dong Wu; Chaohong Hu; Runde Zhou (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A fully-integrated CMOS UWB transceiver for ultra-low-power short-range application. - Mengmeng Liu; Sheng Zhang 003; Shuo Wang; Runde Zhou (Int. J. Circuit Theory Appl., 2011)