Bounds on Net Delays for Physical Design of Fast Circuits. - Habib Youssef; Rung-Bin Lin; Eugene Shragowitz (VLSI, 1991)

Fuzzy Logic Approach to Placement Problem. - Rung-Bin Lin; Eugene Shragowitz (DAC, 1992)

An adaptive timing-driven placement for high performance VLSIs. - Suphachai Sutanthavibul; Eugene Shragowitz; Rung-Bin Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Fuzzy logic approach to VLSI placement. - Eric Q. Kang; Rung-Bin Lin; Eugene Shragowitz (IEEE Trans. Very Large Scale Integr. Syst., 1994)

A New Statistical Approach to Timing Analysis of VLSI Circuits. - Rung-Bin Lin; Meng-Chiou Wu (VLSI Design, 1998)

Low Power CMOS Off-Chip Drivers with Slew-rate Difference. - Rung-Bin Lin; Jinq-Chang Chen (ASP-DAC, 1999)

Benchmark Circuits Improve the Quality of a Standard Cell Library. - Rung-Bin Lin; Isaac Shuo-Hsiu Chou; Chi-Ming Tsai (ASP-DAC, 1999)

Weight-Based Bus-Invert Coding for Low-Power Applications. - Rung-Bin Lin; Chi-Ming Tsai (ASP-DAC/VLSI Design, 2002)

An Adaptive Interconnect-Length Driven Placer. - Chi-Ming Tsai; Kun-Tien Kuo; Chyi-Hui Hong; Rung-Bin Lin (ASP-DAC/VLSI Design, 2002)

Comments on "Filling algorithms and analyses for layout density control". - Rung-Bin Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Theoretical analysis of bus-invert coding. - Rung-Bin Lin; Chi-Ming Tsai (IEEE Trans. Very Large Scale Integr. Syst., 2002)

A Low Power-Delay Product Page-Based Address Bus Coding Method. - Chi-Ming Tsai; Guang-Wan Liao; Rung-Bin Lin (VLSI Design, 2003)

Multi-layer constrained via minimization with conjugate conflict continuation graphs. - Rung-Bin Lin; Shuyu Chen (ISCAS (4), 2004)

Reticle floorplanning of flexible chips for multi-project wafers. - Meng-Chiou Wu; Rung-Bin Lin (ACM Great Lakes Symposium on VLSI, 2005)

A divide-and-conquer approach to estimating minimum/maximum leakage current. - Guang-Wan Liao; Ja-Shong Feng; Rung-Bin Lin (ISCAS (5), 2005)

Coupling reduction analysis of bus-invert coding. - Rung-Bin Lin (ISCAS (6), 2005)

Multiple project wafers for medium-volume IC production. - Meng-Chiou Wu; Rung-Bin Lin (ISCAS (5), 2005)

Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers. - Meng-Chiou Wu; Rung-Bin Lin (ISQED, 2005)

A Comparative Study on Dicing of Multiple Project Wafers. - Meng-Chiou Wu; Rung-Bin Lin (ISVLSI, 2005)

Design space exploration for minimizing multi-project wafer production cost. - Rung-Bin Lin; Meng-Chiou Wu; Wei-Chiu Tseng; Ming-Hsine Kuo; Tsai-Ying Lin; Shr-Cheng Tsai (ASP-DAC, 2006)

Is more redundancy better for on-chip bus encoding. - Hsun-Chieh Yu; Rung-Bin Lin (ISCAS, 2006)

Double-via-driven standard cell library design. - Tsai-Ying Lin; Tsung-Han Lin; Hui-Hsiang Tung; Rung-Bin Lin (DATE, 2007)

Reticle Exposure Plans for Multi-Project Wafers. - Rung-Bin Lin; Da-Wei Hsu; Ming-Hsine Kuo; Meng-Chiou Wu (DDECS, 2007)

Conjugate conflict continuation graphs for multi-layer constrained via minimization. - Rung-Bin Lin; Shuyu Chen (Inf. Sci., 2007)

Reticle Design for Minimizing Multiproject Wafer Production Cost. - Rung-Bin Lin; Meng-Chiou Wu; Shih-Cheng Tsai (IEEE Trans Autom. Sci. Eng., 2007)

Router and cell library co-development for improving redundant via insertion at pins. - Wei-Chiu Tseng; Yu-Hsing Chen; Rung-Bin Lin (ICCD, 2008)

Standard Cell Like Via-Configurable Logic Block for Structured ASICs. - Mei-Chen Li; Hui-Hsiang Tung; Chien-Chung Lai; Rung-Bin Lin (ISVLSI, 2008)

Variable-sized object packing and its applications to instruction cache design. - Rung-Bin Lin (Comput. Electr. Eng., 2008)

Power Reduction during Scan Testing Based on Multiple Capture Technique. - Lung-Jen Lee; Wang-Dauh Tseng; Rung-Bin Lin (IEICE Trans. Electron., 2008)

Finding Dicing Plans for Multiple Project wafers fabricated with Shuttle Mask. - Meng-Chiou Wu; Rung-Bin Lin (J. Circuits Syst. Comput., 2008)

Inter-Wire Coupling Reduction Analysis of Bus-Invert Coding. - Rung-Bin Lin (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Chip placement in a reticle for multiple-project wafer fabrication. - Meng-Chiou Wu; Rung-Bin Lin; Shih-Cheng Tsai (ACM Trans. Design Autom. Electr. Syst., 2008)

A Multi-dimensional Pattern Run-Length Method for Test Data Compression. - Lung-Jen Lee; Wang-Dauh Tseng; Rung-Bin Lin; Chen-Lun Lee (Asian Test Symposium, 2009)

Deterministic Built-In Self-Test Using Multiple Linear Feedback Shift Registers for Low-Power Scan Testing. - Lung-Jen Lee; Wang-Dauh Tseng; Rung-Bin Lin; Chi-Wei Yu (Asian Test Symposium, 2009)

Context-aware Post Routing Redundant Via Insertion. - Po-Heng Chu; Rung-Bin Lin; Da-Wei Hsu; Yu-Hsing Chen; Wei-Chiu Tseng (ISVLSI, 2009)

Power gating design for standard-cell-like structured ASICs. - Sin-Yu Chen; Rung-Bin Lin; Hui-Hsiang Tung; Kuen-Wey Lin (DATE, 2010)

Via configurable three-input lookup-tables for structured ASICs. - Yu-Chen Chen; Hou-Yu Pang; Kuen-Wey Lin; Rung-Bin Lin; Hui-Hsiang Tung; Shih-Chieh Su (ACM Great Lakes Symposium on VLSI, 2010)

Clock routing for structured ASICs with via-configurable fabrics. - Rung-Bin Lin; I-Wei Lee; Wen-Hao Chen (ISQED, 2010)

Deterministic built-in self-test using multiple linear feedback shift registers for test power and test volume reduction. - Wang-Dauh Tseng; Lung-Jen Lee; Rung-Bin Lin (IET Comput. Digit. Tech., 2010)

Clock gating optimization with delay-matching. - Shih-Jung Hsu; Rung-Bin Lin (DATE, 2011)

Rover: routing on via-configurable fabrics for standard-cell-like structured ASICs. - Liang-Chi Lai; Hsih-Hang Chang; Rung-Bin Lin (ACM Great Lakes Symposium on VLSI, 2011)

Design and analysis of via-configurable routing fabrics for structured ASICs. - Hsin-Pei Tsai; Rung-Bin Lin; Liang-Chi Lai (DATE, 2012)

$2^{n}$ Pattern Run-Length for Test Data Compression. - Lung-Jen Lee; Wang-Dauh Tseng; Rung-Bin Lin; Cheng-Ho Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Standard Cell Like Via-Configurable Logic Blocks for Structured ASIC in an Industrial Design Flow. - Hui-Hsiang Tung; Rung-Bin Lin; Mei-Chen Li; Tsung-Han Heish (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Slack budgeting and slack to length converting for multi-bit flip-flop merging. - Chia-Chieh Lu; Rung-Bin Lin (DATE, 2013)

Relocatable and resizable SRAM synthesis for via configurable structured ASIC. - Hsin-Hung Liu; Rung-Bin Lin; I-Lun Tseng (ISQED, 2013)

Logic block and design methodology for via-configurable structured ASIC using dual supply voltages. - Ta-Kai Lin; Kuen-Wey Lin; Chang-Hao Chiu; Rung-Bin Lin (ACM Great Lakes Symposium on VLSI, 2014)

Transition inversion coding with parity check for off-chip serial transmission. - Jian Zeng; Jian-Yang Zhou; Rung-Bin Lin (ICECS, 2014)

Simultaneous transistor pairing and placement for CMOS standard cells. - Ang Lu; Hsueh-Ju Lu; En-Jang Jang; Yu-Po Lin; Chun-Hsiang Hung; Chun-Chih Chuang; Rung-Bin Lin (DATE, 2015)

Overview of the 2015 CAD Contest at ICCAD. - Natarajan Viswanathan; Shih-Hsu Huang; Rung-Bin Lin; Myung-Chul Kim (ICCAD, 2015)

A router for via configurable structured ASIC with standard cells and relocatable IPs. - Chiung-Chih Ho; Hsin-Pei Tsai; Liang-Chi Lai; Rung-Bin Lin (ISQED, 2015)

Multiple-patterning lithography-aware routing for standard cell layout synthesis. - Kuen-Wey Lin; Yih-Lang Li; Rung-Bin Lin (APCCAS, 2016)

Practical ILP-based routing of standard cells. - Hsueh-Ju Lu; En-Jang Jang; Ang Lu; Yu Ting Zhang; Yu-He Chang; Chi-Hung Lin; Rung-Bin Lin (DATE, 2016)

Overview of the 2016 CAD contest at ICCAD. - Shih-Hsu Huang; Rung-Bin Lin; Myung-Chul Kim; Shigetoshi Nakatake (ICCAD, 2016)

Design Space Exploration of FinFETs with Double Fin Heights for Standard Cell Library. - Chi-Hung Lin; Chia-Shiang Chen; Yu-He Chang; Yu Ting Zhang; Shang-Rong Fang; Santanu Santra; Rung-Bin Lin (ISVLSI, 2016)

A Maze Routing-Based Algorithm for ML-OARST with Pre-Selecting and Re-Building Steiner Points. - Kuen-Wey Lin; Yeh-Sheng Lin; Yih-Lang Li; Rung-Bin Lin (ACM Great Lakes Symposium on VLSI, 2017)

Overview of the 2017 CAD contest at ICCAD: Invited paper. - Myung-Chul Kim; Shih-Hsu Huang; Rung-Bin Lin; Shigetoshi Nakatake (ICCAD, 2017)

On Benchmarking Pin Access for Nanotechnology Standard Cells. - Shang-Rong Fang; Cheng-Wei Tai; Rung-Bin Lin (ISVLSI, 2017)

Recognition of regular layout structures. - Yu-Cheng Chiang; Shr-Cheng Tsai; Rung-Bin Lin (ISQED, 2018)

Designing and Benchmarking of Double-Row Height Standard Cells. - Yu-Xiang Chiang; Cheng-Wei Tai; Shang-Rong Fang; Kai-Chun Peng; Yuan-Dar Chung; Jin-Kai Yang; Rung-Bin Lin (ISVLSI, 2018)

A Maze Routing-Based Methodology With Bounded Exploration and Path-Assessed Retracing for Constrained Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction. - Kuen-Wey Lin; Yeh-Sheng Lin; Yih-Lang Li; Rung-Bin Lin (ACM Trans. Design Autom. Electr. Syst., 2018)

Impact of Double-Row Height Standard Cells on Placement and Routing. - Rung-Bin Lin; Yu-Xiang Chiang (ISQED, 2019)

Morphed Standard Cell Layouts for Pin Length Reduction. - Cheng-Wei Tai; Rung-Bin Lin (ISVLSI, 2019)

Engineering a Standard Cell Library for an Industrial Router with ASAP7 PDK. - Yuan-Dar Chung; Rung-Bin Lin (ISVLSI, 2020)

Six-track Standard Cell Libraries with Fin Depopulation, Contact over Active Gate, and Narrower Diffusion Break in 7nm Technology. - Tzu-Hsuan Wang; Chih-Chun Hsu; Li Kao; Bing-Yu Li; Tung-Chun Wu; Tsao-Hsuan Peng; Rung-Bin Lin (ISQED, 2021)

Improving Pin Accessibility of Standard Cell Libraries in 7nm Technology. - Tsao-Hsuan Peng; Chih-Chun Hsu; Po-Chun Wang; Rung-Bin Lin (ISQED, 2022)

Improving Pin Accessibility of Standard Cells under Power/Ground Stripes. - Pei-Sheng Lu; Rung-Bin Lin (NEWCAS, 2023)

Standard Cells with Inverted Inputs in 7nm Technology. - Tung-Chun Wu; Rung-Bin Lin (APCCAS, 2024)

Engineering ASAP7 PDK with Buried Power Rail and Backside Metal Technologies. - Wen-Cheng Yang; Ting-An Jian; Yu-Cheng Lin; Rung-Bin Lin (APCCAS, 2024)

Sub-10nm Standard Cell Library Design Methodology for On-Grid Pin Accesses. - Rung-Bin Lin; Pei-Sheng Lu (ISCAS, 2024)

Routing Intent Aware Pin Access Point Selection for Standard Cell Designs. - Po-Chun Wang; Kai-Jie Ton; Rung-Bin Lin (ISQED, 2024)

A 4.5-Track Standard Cell Library with Buried Power Rails in 7nm Node. - Kai-Jie Tong; Ting-An Jian; Shang-Mou Zhou; Yi-Jia Wu; Bo-Xiang Yang; Meng-Ru Lin; Ming-Yi Huang; Shi-Xian Tang; Ya-Zhu Yang; Zheng-Jie Peng; Yu-Cheng Lin; Rung-Bin Lin (ISCAS, 2025)

Subitizing-Inspired_Large_Language_Models_for_Floorplanning. - Shao-Chien Lu; Chen-Chen Yeh; Hui-Lin Cho; Yu-Cheng Lin; Rung-Bin Lin (CoRR, 2025)