Decomposition of Finite State Machines for Area, Delay Minimization. - Rupesh S. Shelar; Madhav P. Desai; H. Narayanan (ICCD, 1999)

Parameterized Reusable Component Library Methodology. - Rupesh S. Shelar; Sacheendra Nath; Jagmohan S. Nanaware (EUROMICRO, 2000)

Recursive Bipartitioning of BDDs for Performance Driven Synthesis of Pass Transistor Logic Circuits. - Rupesh S. Shelar; Sachin S. Sapatnekar (ICCAD, 2001)

Efficient Layout Synthesis Algorithm for Pass Transistor Logic Circuits. - Rupesh S. Shelar; Sachin S. Sapatnekar (IWLS, 2002)

An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis. - Rupesh S. Shelar; Sachin S. Sapatnekar (ASP-DAC/VLSI Design, 2002)

A predictive distributed congestion metric and its application to technology mapping. - Rupesh S. Shelar; Sachin S. Sapatnekar; Prashant Saxena; Xinning Wang (ISPD, 2004)

An efficient technology mapping algorithm targeting routing congestion under delay constraints. - Rupesh S. Shelar; Prashant Saxena; Xinning Wang; Sachin S. Sapatnekar (ISPD, 2005)

A predictive distributed congestion metric with application to technology mapping. - Rupesh S. Shelar; Sachin S. Sapatnekar; Prashant Saxena; Xinning Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

BDD decomposition for delay oriented pass transistor logic synthesis. - Rupesh S. Shelar; Sachin S. Sapatnekar (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints. - Rupesh S. Shelar; Prashant Saxena; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Routing Congestion in VLSI Circuits - Estimation and Optimization. - Prashant Saxena; Rupesh S. Shelar; Sachin S. Sapatnekar (Springer, 2007)

An efficent clustering algorithm for low power clock tree synthesis. - Rupesh S. Shelar (ISPD, 2007)

Delay-optimal simultaneous technology mapping and placement with applications to timing optimization. - Yifang Liu; Rupesh S. Shelar; Jiang Hu (ICCAD, 2008)

Estimation of Routing Congestion. - Rupesh S. Shelar; Prashant Saxena (Handbook of Algorithms for Physical Design Automation, 2008)

An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors. - Rupesh S. Shelar (ISPD, 2009)

Routing With Constraints for Post-Grid Clock Distribution in Microprocessors. - Rupesh S. Shelar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Simultaneous Technology Mapping and Placement for Delay Minimization. - Yifang Liu; Rupesh S. Shelar; Jiang Hu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

A Fast and Near-Optimal Clustering Algorithm for Low-Power Clock Tree Synthesis. - Rupesh S. Shelar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Impact of Local Interconnects on Timing and Power in a High Performance Microprocessor. - Rupesh S. Shelar; Marek Patyra (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

An Algorithm for Delay Optimal Logic Replication for FPGAs Accounting for Combinational Loops. - Rupesh S. Shelar (FPGA, 2020)