A methodology for formal design of hardware control with application to cache coherence protocols. - Cindy Eisner; Irit Shitsevalov; Russ Hoover; Wayne G. Nation; Kyle L. Nelson; Ken Valk (DAC, 2000)

A wire-speed powerTM processor: 2.3GHz 45nm SOI with 16 cores and 64 threads. - Charles L. Johnson; David H. Allen; Jeffrey D. Brown; Steve Vanderwiel; Russ Hoover; Heather D. Achilles; Chen-Yong Cher; George A. May; Hubertus Franke; Jimi Xenidis; Claude Basso (ISSCC, 2010)