Run-time power estimation in high performance microprocessors. - Russ Joseph; Margaret Martonosi (ISLPED, 2001)

Control Techniques to Eliminate Voltage Emergencies in High Performance Processors. - Russ Joseph; David M. Brooks; Margaret Martonosi (HPCA, 2003)

Wavelet Analysis for Microprocessor Design: Experiences with Wavelet-Based dI/dt Characterization. - Russ Joseph; Zhigang Hu; Margaret Martonosi (HPCA, 2004)

Spectral analysis for characterizing program power and performance. - Russ Joseph; Margaret Martonosi; Zhigang Hu (ISPASS, 2004)

Process variation aware cache leakage management. - Ke Meng; Russ Joseph (ISLPED, 2006)

Power deregulation: eliminating off-chip voltage regulation circuitry from embedded systems. - Seunghoon Kim; Robert P. Dick; Russ Joseph (CODES+ISSS, 2007)

Understanding voltage variations in chip multiprocessors using a distributed power-delivery network. - Meeta Sharma Gupta; Jarod L. Oatley; Russ Joseph; Gu-Yeon Wei; David M. Brooks (DATE, 2007)

Modeling and Characterizing Power Variability in Multicore Architectures. - Ke Meng; Frank Huebbers; Russ Joseph; Yehea I. Ismail (ISPASS, 2007)

Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors. - David M. Brooks; Robert P. Dick; Russ Joseph; Li Shang (IEEE Micro, 2007)

Multi-optimization power management for chip multiprocessors. - Ke Meng; Russ Joseph; Robert P. Dick; Li Shang (PACT, 2008)

Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management. - Changyun Zhu; Zhenyu (Peter) Gu; Li Shang; Robert P. Dick; Russ Joseph (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Process variation characterization of chip-level multiprocessors. - Lide Zhang; Lan S. Bai; Robert P. Dick; Li Shang; Russ Joseph (DAC, 2009)

Exploiting Locality to Improve Circuit-Level Timing Speculation. - Jing Xin; Russ Joseph (IEEE Comput. Archit. Lett., 2009)

A Case for Alternative Nested Paging Models for Virtualized Systems. - Giang Hoang; Chang Bae; Jack Lange; Lide Zhang; Peter A. Dinda; Russ Joseph (IEEE Comput. Archit. Lett., 2010)

Exploring circuit timing-aware language and compilation. - Giang Hoang; Robby Bruce Findler; Russ Joseph (ASPLOS, 2011)

Efficient parameter variation sampling for architecture simulations. - Feng Lu; Russ Joseph; Goce Trajcevski; Song Liu (DATE, 2011)

Identifying and predicting timing-critical instructions to boost timing speculation. - Jing Xin; Russ Joseph (MICRO, 2011)

Spatially- and temporally-adaptive communication protocols for zero-maintenance sensor networks relying on opportunistic energy scavenging. - Xuejing He; Robert P. Dick; Russ Joseph (CODES+ISSS, 2012)

Virtual-machine-based emulation of future generation high-performance computing systems. - Patrick G. Bridges; Dorian C. Arnold; Kevin T. Pedretti; Madhav Suresh; Feng Lu; Peter A. Dinda; Russ Joseph; Jack Lange (Int. J. High Perform. Comput. Appl., 2012)

Reliability Modeling and Management of Nanophotonic On-Chip Networks. - Zheng Li; Moustafa Mohamed; Xi Chen; Eric Dudley; Ke Meng; Li Shang; Alan Rolf Mickelson; Russ Joseph; Manish Vachharajani; Brian Schwartz; Yihe Sun (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Embedded system and application aware design of deregulated energy delivery systems. - Xuejing He; Robert P. Dick; Russ Joseph (CASES, 2015)

Exploration of associative power management with instruction governed operation for ultra-low power design. - Tianyu Jia; Yuanbo Fan; Russ Joseph; Jie Gu 001 (DAC, 2016)

Enabling Deep Voltage Scaling in Delay Sensitive L1 Caches. - Chao Yan; Russ Joseph (DSN, 2016)

Greybox Design Methodology: A Program Driven Hardware Co-optimization with Ultra-Dynamic Clock Management. - Tianyu Jia; Russ Joseph; Jie Gu 001 (DAC, 2017)

(Invited) Software-guided greybox design methodology with integrated power and clock management. - Tianyu Jia; Yuanbo Fan; Russ Joseph; Jie Gu 001 (MWSCAS, 2017)

D2M: data-driven model for fast and accurate timing error simulation in statically scheduled microprocessors. - Yuanbo Fan; Russ Joseph (SummerSim, 2017)

Compiler-guided instruction-level clock scheduling for timing speculative processors. - Yuanbo Fan; Tianyu Jia; Jie Gu 001; Simone Campanoni; Russ Joseph (DAC, 2018)

An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor. - Tianyu Jia; Russ Joseph; Jie Gu 001 (ESSCIRC, 2018)

Cocoa: synergistic cache compression and error correction in capacity sensitive last level caches. - Chao Yan; Russ Joseph (MEMSYS, 2018)

Time squeezing for tiny devices. - Yuanbo Fan; Simone Campanoni; Russ Joseph (ISCA, 2019)

An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution. - Tianyu Jia; Russ Joseph; Jie Gu 001 (ISSCC, 2019)

An Instruction-Driven Adaptive Clock Management Through Dynamic Phase Scaling and Compiler Assistance for a Low Power Microprocessor. - Tianyu Jia; Russ Joseph; Jie Gu 001 (IEEE J. Solid State Circuits, 2019)

NCPU: An Embedded Neural CPU Architecture on Resource-Constrained Low Power Devices for Real-time End-to-End Performance. - Tianyu Jia; Yuhao Ju; Russ Joseph; Jie Gu 001 (MICRO, 2020)

An Adaptive Clock Scheme Exploiting Instruction-Based Dynamic Timing Slack for a GPGPU Architecture. - Tianyu Jia; Yijie Wei; Russ Joseph; Jie Gu 001 (IEEE J. Solid State Circuits, 2020)

Saving Energy with Per-Variable Bitwidth Speculation. - Tommy McMichen; David Dlott; Panitan Wongse-ammat; Nathan Greiner; Hussain Khajanchi; Russ Joseph; Simone Campanoni (ASPLOS (2), 2025)