Minimax optimization of two-dimensional focused nonuniformly spaced arrays. - Russell P. Kraft; John F. McDonald 001; F. Ahlgren (ICASSP, 1979)

Homomorphic signal dereverberation for a phased array imaging system. - Russell P. Kraft; John F. McDonald 001; J. Erkes (ICASSP, 1982)

A very wide bandwidth digital VCO using quadrature frequency multiplication and division implemented in AlGaAs/GaAs HBT's. - Pete M. Campbell; Hans J. Greub; Atul Garg; Sam A. Steidl; Steven R. Carlough; Matthew W. Ernest; Robert F. Philhower; Cliff A. Maier; Russell P. Kraft; John F. McDonald 001 (IEEE Trans. Very Large Scale Integr. Syst., 1998)

Accurate high-speed performance prediction for full differential current-mode logic: the effect of dielectric anisotropy. - Atul Garg; Y. L. Le Coz; Hans J. Greub; R. B. Iverson; Robert F. Philhower; Pete M. Campbell; Cliff A. Maier; Sam A. Steidl; Matthew W. Ernest; Russell P. Kraft; Steven R. Carlough; J. W. Perry; et al. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

A 2-GHz clocked AlGaAs/GaAs HBT byte-slice datapath chip. - Steven R. Carlough; Robert A. Philhower; Cliff A. Maier; Sam A. Steidl; Pete M. Campbell; Atul Garg; Kyung-Suc Nah; Matthew W. Ernest; James R. Loy; Thomas W. Krawczyk Jr.; Peter F. Curran; Russell P. Kraft; et al. (IEEE J. Solid State Circuits, 2000)

Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs. - Bryan S. Goda; Russell P. Kraft; Steven R. Carlough; Thomas W. Krawczyk Jr.; John F. McDonald 001 (FPL, 2001)

Gigahertz FPGAs with New Power Saving Techniques and Decoding Logic. - Channakeshav; Kuan Zhou; Russell P. Kraft; John F. McDonald 001 (Evolvable Hardware, 2002)

Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques. - Channakeshav; Kuan Zhou; Jong-Ru Guo; Chao You; Bryan S. Goda; Russell P. Kraft; John F. McDonald 001 (FPL, 2002)

Gigahertz SiGe BiCMOS FPGAs with new architectures and novel power management schemes. - Kuan Zhou; Channakeshav; Michael Chu; Jong-Ru Guo; S.-C. Liu; Russell P. Kraft; Chao You; John F. McDonald 001 (FPT, 2002)

A Novel Multi-Speed, Power Saving Architecture for SiGe HBT FPGA. - Jong-Ru Guo; Chao You; Michael Chu; Kuan Zhou; Young Uk Yim; Robert W. Heikaus; Russell P. Kraft; John F. McDonald 001 (Engineering of Reconfigurable Systems and Algorithms, 2003)

A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology. - Jong-Ru Guo; Chao You; Kuan Zhou; Bryan S. Goda; Russell P. Kraft; John F. McDonald 001 (FPGA, 2003)

A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme. - Kuan Zhou; Michael Chu; Chao You; Jong-Ru Guo; Channakeshav; John Mayega; John F. McDonald 001; Russell P. Kraft; Bryan S. Goda (FPGA, 2003)

Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory. - Chao You; Jong-Ru Guo; Russell P. Kraft; Michael Chu; Robert W. Heikaus; Okan Erdogan; Peter F. Curran; Bryan S. Goda; Kuan Zhou; John F. McDonald 001 (FPL, 2003)

3D direct vertical interconnect microprocessors test vehicle. - John Mayega; Okan Erdogan; Paul M. Belemjian; Kuan Zhou; John F. McDonald 001; Russell P. Kraft (ACM Great Lakes Symposium on VLSI, 2003)

A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS technology. - Chao You; Jong-Ru Guo; Russell P. Kraft; Kuan Zhou; Michael Chu; John F. McDonald 001 (ACM Great Lakes Symposium on VLSI, 2003)

The gigahertz FPGA: design consideration and applications. - Jong-Ru Guo; Chao You; Michael Chu; Robert W. Heikaus; Kuan Zhou; Okan Erdogan; Jiedong Diao; Bryan S. Goda; Russell P. Kraft; John F. McDonald 001 (FPGA, 2004)

The 10GHz 4: 1 MUX and 1: 4 DEMUX implemented via the gigahertz SiGe FPGA. - Jong-Ru Guo; Chao You; Peter F. Curran; Michael Chu; Kuan Zhou; Jiedong Diao; A. George; Russell P. Kraft; John F. McDonald 001 (ACM Great Lakes Symposium on VLSI, 2004)

A 11 GHz FPGA with Test Applications. - Chao You; Jong-Ru Guo; Michael Chu; Russell P. Kraft; Bryan S. Goda; John F. McDonald 001 (FPL, 2005)

A High Speed Reconfigurable Gate Array for Gigahertz Applications. - Jong-Ru Guo; Chao You; Michael Chu; Okan Erdogan; Russell P. Kraft; John F. McDonald 001 (ISVLSI, 2005)

12-23 GHz Ultra Wide Tuning Range Voltage-Controlled Ring Oscillator with Hybrid Control Schemes. - Young Uk Yim; John F. McDonald 001; Russell P. Kraft (ISVLSI, 2005)

Predicting the Performance of a 3D Processor-Memory Chip Stack. - Philip Jacob 001; Okan Erdogan; Aamir Zia; Paul M. Belemjian; Russell P. Kraft; John F. McDonald 001 (IEEE Des. Test Comput., 2005)

A 10 GHz 4: 1 MUX and 1: 4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC. - Jong-Ru Guo; Chao You; Kuan Zhou; Michael Chu; Peter F. Curran; Jiedong Diao; Bryan S. Goda; Russell P. Kraft; John F. McDonald 001 (Integr., 2005)

Multi-ghz Sige Bicmos Fpgas with New Architecture and Novel Power Management Techniques. - Kuan Zhou; Jong-Ru Guo; Chao You; John Mayega; Russell P. Kraft; T. Zhang; John F. McDonald 001; Bryan S. Goda (J. Circuits Syst. Comput., 2005)

A 5-10GHz SiGe BiCMOS FPGA with new configurable logic block. - Chao You; Jong-Ru Guo; Russell P. Kraft; Michael Chu; Peter F. Curran; Kuan Zhou; Bryan S. Goda; John F. McDonald 001 (Microprocess. Microsystems, 2005)

SiGe HBT Microprocessor Core Test Vehicle. - Paul M. Belemjian; Okan Erdogan; Russell P. Kraft; John F. McDonald 001 (Proc. IEEE, 2005)

Amdahl's figure of merit, SiGe HBT BiCMOS, and 3D chip stacking. - Philip Jacob 001; Aamir Zia; Okan Erdogan; Paul M. Belemjian; Peng Jin; Jin Woo Kim; Michael Chu; Russell P. Kraft; John F. McDonald 001 (ICCD, 2007)

Silicon germanium programmable circuits for gigahertz applications. - Jong-Ru Guo; Chao You; Mike Chu; Peter F. Curran; Jiedong Diao; Bryan S. Goda; Peng Jin; Russell P. Kraft; John F. McDonald 001 (IET Circuits Devices Syst., 2007)

52 Gb/s 16: 1 transmitter in 0.13 μm SiGe BiCMOS technology. - Young Uk Yim; Peter F. Curran; Michael Chu; John F. McDonald 001; Russell P. Kraft (IET Circuits Devices Syst., 2007)

A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits. - Chao You; Jong-Ru Guo; Russell P. Kraft; Michael Chu; Bryan S. Goda; John F. McDonald 001 (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Thermal analysis for a SiGe HBT 40 watt 32 GHz clock 3D memory processor chip stack using diamond heat spreader layers. - John F. McDonald 001; Okan Erdogan; Philip Jacob 001; Paul M. Belemjian; Alexey Gutin; Aamir Zia; Michael Chu; Jin Woo Kim; Ryan Clarke; Nate DeSimone; Sherry Liu; Russell P. Kraft (3DIC, 2009)

Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks. - Philip Jacob 001; Aamir Zia; Okan Erdogan; Paul M. Belemjian; Jin Woo Kim; Michael Chu; Russell P. Kraft; John F. McDonald 001; Kerry Bernstein (Proc. IEEE, 2009)

A 40 Gs/s Time Interleaved ADC Using SiGe BiCMOS Technology. - Michael Chu; Philip Jacob 001; Jin Woo Kim; Mitchell R. LeRoy; Russell P. Kraft; John F. McDonald 001 (IEEE J. Solid State Circuits, 2010)

Correction to "A 40 GS/s Time Interleaved ADC Using SiGe BiCMOS Technology". - Michael Chu; Philip Jacob 001; Jin Woo Kim; Mitchell R. LeRoy; Russell P. Kraft; John F. McDonald 001 (IEEE J. Solid State Circuits, 2010)

A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration. - Aamir Zia; Philip Jacob 001; Jin Woo Kim; Michael Chu; Russell P. Kraft; John F. McDonald 001 (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Reconfigurable 40 GHz BiCMOS uniform delay crossbar switch for broadband and wide tuning range narrowband applications. - Jin Woo Kim; Michael Chu; Philip Jacob 001; Aamir Zia; Russell P. Kraft; John F. McDonald 001 (IET Circuits Devices Syst., 2011)

Carry Chains for Ultra High-Speed SiGe HBT Adders. - Alexey Gutin; Philip Jacob 001; Michael Chu; Paul M. Belemjian; Mitchell R. LeRoy; Russell P. Kraft; John F. McDonald 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A three-dimensional DRAM using floating body cell in FDSOI devices. - Xuelian Liu; Aamir Zia; Mitchell R. LeRoy; Srikumar Raman; Ryan Clarke; Russell P. Kraft; John F. McDonald 001 (DDECS, 2012)

Design of BiCMOS SRAMs for high-speed SiGe applications. - Xuelian Liu; Mitchell R. LeRoy; Ryan Clarke; Michael Chu; H. O. Aquino; Srikumar Raman; Aamir Zia; Russell P. Kraft; John F. McDonald 001 (IET Circuits Devices Syst., 2014)

Design of High-Speed Register Files Using SiGe HBT BiCMOS Technology. - Xuelian Liu; Srikumar Raman; Ryan Clarke; Mitchell R. LeRoy; Okan Erdogan; Michael Chu; Alexey Gutin; Russell P. Kraft; John F. McDonald 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Thermal Modeling of 3-D Stacked DRAM Over SiGe HBT BiCMOS CPU. - Ryan Clarke; Philip Jacob 001; Okan Erdogan; Paul Belemijian; Srikumar Raman; Mitchell R. LeRoy; Tuhin Guha Neogi; Russell P. Kraft; Diana-Andra Borca-Tasciuc; John F. McDonald 001 (IEEE Access, 2015)

140 Gb/s Serializer Using Clock Doublers in 90 nm SiGe Technology. - Ryan Clarke; Mitchell R. LeRoy; Srikumar Raman; Tuhin Guha Neogi; Russell P. Kraft; John F. McDonald 001 (IEEE J. Solid State Circuits, 2015)