Performance driven reliable link design for networks on chips. - Rutuparna Tamhankar; Srinivasan Murali; Giovanni De Micheli (ASP-DAC, 2005)

NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip. - Davide Bertozzi; Antoine Jalabert; Srinivasan Murali; Rutuparna Tamhankar; Stergios Stergiou; Luca Benini; Giovanni De Micheli (IEEE Trans. Parallel Distributed Syst., 2005)

Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips. - Srinivasan Murali; Rutuparna Tamhankar; Federico Angiolini; Antonio Pullini; David Atienza; Luca Benini; Giovanni De Micheli (SoC, 2006)

Timing-Error-Tolerant Network-on-Chip Design Methodology. - Rutuparna Tamhankar; Srinivasan Murali; Stergios Stergiou; Antonio Pullini; Federico Angiolini; Luca Benini; Giovanni De Micheli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)