Pipelined parallel architecture for high throughput MAP detectors. - Ruwan N. S. Ratnayake; Gu-Yeon Wei; Aleksandar Kavcic (ISCAS (2), 2004)

A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders. - Ruwan N. S. Ratnayake; Erich F. Haratsch; Gu-Yeon Wei (GLOBECOM, 2007)

Serial Sum-Product Architecture for Low-Density Parity-Check Codes. - Ruwan N. S. Ratnayake; Erich F. Haratsch; Gu-Yeon Wei (ICCCN, 2007)

A High-Throughput Maximum a Posteriori Probability Detector. - Ruwan N. S. Ratnayake; Aleksandar Kavcic; Gu-Yeon Wei (IEEE J. Solid State Circuits, 2008)