Switching Activity Models for Power Estimation in FPGA Multipliers. - Ruzica Jevtic; Carlos Carreras; Gabriel Caffarena (ARC, 2007)

Analytical High-Level Power Model for LUT-Based Components. - Ruzica Jevtic; Carlos Carreras (PATMOS, 2008)

A Comparison of Approaches for High-Level Power Estimation of LUT-Based DSP Components. - Ruzica Jevtic; Carlos Carreras; Domenik Helms (ReConFig, 2008)

Floorplan-based FPGA interconnect power estimation in DSP circuits. - Ruzica Jevtic; Carlos Carreras; Vukasin Pejovic (SLIP, 2009)

Power Estimation of Embedded Multiplier Blocks in FPGAs. - Ruzica Jevtic; Carlos Carreras (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Power estimation of dividers implemented in FPGAs. - Ruzica Jevtic; Bojan Jovanovic; Carlos Carreras (ACM Great Lakes Symposium on VLSI, 2011)

Technology Variability From a Design Perspective. - Borivoje Nikolic; Ji-Hoon Park; Jaehwa Kwak; Bastien Giraud; Zheng Guo; Liang-Teck Pang; Seng Oon Toh; Ruzica Jevtic; Kun Qian 014; Costas J. Spanos (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Power Measurement Methodology for FPGA Devices. - Ruzica Jevtic; Carlos Carreras (IEEE Trans. Instrum. Meas., 2011)

A complete dynamic power estimation model for data-paths in FPGA DSP designs. - Ruzica Jevtic; Carlos Carreras (Integr., 2012)

Memory optimization in FPGA-accelerated scientific codes based on unstructured meshes. - Pablo Barrio 001; Carlos Carreras; Juan A. López; Óscar Robles; Ruzica Jevtic; Roberto Sierra (J. Syst. Archit., 2014)

Binary Division Power Models for High-Level Power Estimation of FPGA-Based DSP Circuits. - Bojan Jovanovic; Ruzica Jevtic; Carlos Carreras (IEEE Trans. Ind. Informatics, 2014)

Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking. - Yunsup Lee; Brian Zimmer; Andrew Waterman; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Henry Cook; Rimas Avizienis; et al. (Hot Chips Symposium, 2015)

A MEMS microphone interface based on a CMOS LC oscillator and a digital sigma-delta modulator. - Fernando Cardes; Ruzica Jevtic; Luis Hernández 003; Andreas Wiesbauer; Dietmar Sträußnigg; Richard Gaggl (ISCAS, 2015)

Fully integrated DC-DC converter and a 0.4V 32-bit CPU with timing-error prevention supplied from a prototype 1.55V Li-ion battery. - Matthew J. Turnquist; Markus Hiienkari; Jani Mäkipää; Ruzica Jevtic; Elina Pohjalainen; Tanja Kallio; Lauri Koskinen (VLSIC, 2015)

A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. - Brian Zimmer; Yunsup Lee; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Hanh-Phuc Le; Po-Hung Chen; Nicholas Sutardja; et al. (VLSIC, 2015)

Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors. - Ruzica Jevtic; Hanh-Phuc Le; Milovan Blagojevic; Stevo Bailey; Krste Asanovic; Elad Alon; Borivoje Nikolic (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI. - Brian Zimmer; Yunsup Lee; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Steven Bailey; Milovan Blagojevic; Pi-Feng Chiu; Hanh-Phuc Le; Po-Hung Chen; Nicholas Sutardja; et al. (IEEE J. Solid State Circuits, 2016)

An Agile Approach to Building RISC-V Microprocessors. - Yunsup Lee; Andrew Waterman; Henry Cook; Brian Zimmer; Ben Keller; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Rimas Avizienis; et al. (IEEE Micro, 2016)

Reconfigurable Switched Capacitor DC-DC Converter for Improved Security in IoT Devices. - Ruzica Jevtic; Marko Ylitolva; Lauri Koskinen (PATMOS, 2018)

EM Side-Channel Countermeasure for Switched-Capacitor DC-DC Converters Based on Amplitude Modulation. - Ruzica Jevtic; Marko Ylitolva; Clara Calonge; Martti Ojanen; Tero Säntti; Lauri Koskinen (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Side-channel Attack Countermeasure Based on Power Supply Modulation. - Ruzica Jevtic; Pablo Pérez-Tirador; Carmen Cabezaolias; Pablo Carnero; Gabriel Caffarena (EUSIPCO, 2022)

Methodology for Complete Decorrelation of Power Supply EM Side-Channel Signal and Sensitive Data. - Ruzica Jevtic; Mariano García Otero (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

The effect of ECG data variability on side-channel attack success rate in wearable devices. - Pablo Pérez-Tirador; Ruzica Jevtic; Carmen Cabezaolias; Teresa Romero; Abraham Otero; Gabriel Caffarena (Integr., 2025)

Side-channel attacks and countermeasures for heart rate retrieval from ECG characterization device. - Pablo Pérez-Tirador; Madhav P. Desai; Alejandro Rodriguez; Elena Berral; Teresa Romero; Gabriel Caffarena; Ruzica Jevtic (Int. J. Inf. Sec., 2025)