A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS. - Peter J. Klim; John Barth 001; William R. Reohr; David Dick; Gregory Fredeman; Gary Koch; Hien M. Le; Aditya Khargonekar; Pamela Wilcox; John Golz; Jente B. Kuang; Abraham Mathews; et al. (IEEE J. Solid State Circuits, 2009)

An 8MB level-3 cache in 32nm SOI with column-select aliasing. - Don Weiss; Michael Dreesen; Michael Ciraula; Carson Henrion; Chris Helt; Ryan Freese; Tommy Miles; Anita Karegar; Russell Schreiber; Bryan Schneller; John J. Wuu (ISSCC, 2011)