Correlations between BTI-Induced Degradations and Process Variations on ASICs and FPGAs. - Michitarou Yabuuchi; Ryo Kishida; Kazutoshi Kobayashi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Negative bias temperature instability caused by plasma induced damage in 65 nm bulk and Silicon on thin BOX (SOTB) processes. - Ryo Kishida; Azusa Oshima; Kazutoshi Kobayashi (IRPS, 2015)

Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS. - Takuya Komawaki; Michitarou Yabuuchi; Ryo Kishida; Jun Furuta; Takashi Matsumoto; Kazutoshi Kobayashi (ICICDT, 2017)

Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model. - Takuya Komawaki; Michitarou Yabuuchi; Ryo Kishida; Jun Furuta; Takashi Matsumoto; Kazutoshi Kobayashi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Novel C-2αC Ladder Based Non-binary DAC for SAR-ADC Using Unit Capacitors. - Satoshi Sekine; Tatsuji Matsuura; Ryo Kishida; Akira Hyogo (ISPACS, 2018)

Temperature Dependence of Bias Temperature Instability (BTI) in Long-term Measurement by BTI-sensitive and -insensitive Ring Oscillators Removing Environmental Fluctuation. - Takuya Asuke; Ryo Kishida; Jun Furuta; Kazutoshi Kobayashi (ASICON, 2019)

Compact Modeling of NBTI Replicating AC Stress / Recovery from a Single-shot Long-term DC Measurement. - Takumi Hosaka; Shinichi Nishizawa; Ryo Kishida; Takashi Matsumoto; Kazutoshi Kobayashi (IOLTS, 2019)

Investigation of Hybrid ADC Combined with First-order Feedforward Incremental and SAR ADCs. - Yuichiro Kobayashi; Tatsuji Matsuura; Ryo Kishida; Akira Hyogo (ISPACS, 2019)

Duty Ratio and Capacitance Analysis of AC/DC Converter without Current Control Circuit. - Yuki Tanaka; Tatsuji Matsuura; Ryo Kishida; Akira Hyogo (ISPACS, 2019)

Examination of Incremental ADC with SAR ADC to Reduce Conversion Time with High Accuracy. - Yuichiro Unno; Tatsuji Matsuura; Ryo Kishida; Akira Hyogo (ISPACS, 2019)

Universal NBTI Compact Model Replicating AC Stress/Recovery from a Single-shot Long-term DC Measurement. - Takumi Hosaka; Shinichi Nishizawa; Ryo Kishida; Takashi Matsumoto; Kazutoshi Kobayashi (IPSJ Trans. Syst. LSI Des. Methodol., 2020)

Bias Temperature Instability Depending on Body Bias through Buried Oxide (BOX) Layer in a 65 nm Fully-Depleted Silicon-On-Insulator Process. - Ryo Kishida; Ikuo Suda; Kazutoshi Kobayashi (IRPS, 2021)

Digital Calibration Algorithm of Conversion Error Influenced by Parasitic Capacitance in C-C SAR-ADC Based on γ-Estimation. - Satoshi Sekine; Tatsuji Matsuura; Ryo Kishida; Akira Hyogo (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

An Aging Degradation Suppression Scheme at Constant Performance by Controlling Supply Voltage and Body Bias in a 65 nm Fully-Depleted Silicon-On-Insulator Process. - Ikuo Suda; Ryo Kishida; Kazutoshi Kobayashi (IRPS, 2022)

Ring Oscillators with identical Circuit Structure to Measure Bias Temperature Instability. - Daisuke Kikuta; Ryo Kishida; Kazutoshi Kobayashi (ASICON, 2023)

A Fractional-N PLL for Multi-phase Clock Generation with Loop Bandwidth Enhancement. - Reo Nagasue; Isamu Mizuno; Ryo Kishida; Tatsuya Iwata; Takefumi Yoshikawa (ISCAS, 2024)

A Power Reduction Scheme by Arithmetic Format Conversion for a DSP to Estimate Qubit States Under 4K Cryogenic Environment. - Takashi Imagawa; Ryo Kishida; Yuki Koyama 005; Kazutoshi Kobayashi; Takefumi Miyoshi (QCE, 2024)

Investigation of the Time-Dependent BTI-induced Degradation Distribution for Ring Oscillators in Ultra-Long-Term Stress Conditions. - Tomoharu Kishita; Ryo Kishida; Kazutoshi Kobayashi (IRPS, 2025)

An Expandable Digital Delay Line using Phase Interpolator with Duty Cycle Correction Capability. - Shinya Nagasaki; Ryo Kishida; Takefumi Yoshikawa (ISCAS, 2025)