An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane. - Koji Fukuda; Hiroki Yamashita; Fumio Yuki; Masayoshi Yagyu; Ryo Nemoto; Takashi Takemoto; Tatsuya Saito; Norio Chujo; Keiichi Yamamoto; Hisaaki Kanai; Atsuhiro Hayashi (ISSCC, 2008)

10Gb/s receiver with track-and-hold-type linear phase detector and charge-redistribution 1st-order ΔΣ modulator. - Koji Fukuda; Hiroki Yamashita; Fumio Yuki; Goichi Ono; Ryo Nemoto; Eiichi Suzuki; Takashi Takemoto; Tatsuya Saito (ISSCC, 2009)

A 10-Gb/s Receiver With Track-and-Hold-Type Linear Phase Detector and Charge-Redistribution First-Order ΔΣ Modulator in 90-nm CMOS. - Koji Fukuda; Hiroki Yamashita; Fumio Yuki; Goichi Ono; Ryo Nemoto; Eiichi Suzuki; Takashi Takemoto; Masashi Kono; Tatsuya Saito (IEEE J. Solid State Circuits, 2009)

A 12.3mW 12.5Gb/s complete transceiver in 65nm CMOS. - Koji Fukuda; Hiroki Yamashita; Goichi Ono; Ryo Nemoto; Eiichi Suzuki; Takashi Takemoto; Fumio Yuki; Tatsuya Saito (ISSCC, 2010)

A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process. - Koji Fukuda; Hiroki Yamashita; Goichi Ono; Ryo Nemoto; Eiichi Suzuki; Noboru Masuda; Takashi Takemoto; Fumio Yuki; Tatsuya Saito (IEEE J. Solid State Circuits, 2010)

10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link. - Goichi Ono; Keiki Watanabe; Takashi Muto; Hiroki Yamashita; Koji Fukuda; Noboru Masuda; Ryo Nemoto; Eiichi Suzuki; Takashi Takemoto; Fumio Yuki; Masayoshi Yagyu; Hidehiro Toyoda; et al. (ISSCC, 2011)

A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link. - Goichi Ono; Keiki Watanabe; Takashi Muto; Hiroki Yamashita; Koji Fukuda; Noboru Masuda; Ryo Nemoto; Eiichi Suzuki; Takashi Takemoto; Fumio Yuki; Masayoshi Yagyu; Hidehiro Toyoda; et al. (IEEE J. Solid State Circuits, 2011)