A 1-Mbit BiCMOS DRAM using temperature-compensation circuit techniques. - Goro Kitsukawa; Kiyoo Itoh 001; Ryoichi Hori; Yoshiki Kawajiri; Takao Watanabe; Takayuki Kawahara; Tetsuro Matsumoto; Yutaka Kobayashi (IEEE J. Solid State Circuits, 1989)

Comparison of CMOS and BiCMOS 1-Mbit DRAM performance. - Takao Watanabe; Goro Kitsukawa; Yoshiki Kawajiri; Kiyoo Itoh 001; Ryoichi Hori; Yoshiaki Ouchi; Takayuki Kawahara; Tetsuro Matsumoto (IEEE J. Solid State Circuits, 1989)

Substrate current reduction techniques for BiCMOS DRAM. - Takayuki Kawahara; Goro Kitsukawa; Hisayuki Higuchi; Yoshiki Kawajiri; Takao Watanabe; Kiyoo Itoh 001; Ryoichi Hori; Yutaka Kobayashi; Tetsuro Matsumoto (IEEE J. Solid State Circuits, 1989)