A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes. - Hidehiro Shiga; Daisaburo Takashima; Shinichiro Shiratake; Katsuhiko Hoya; Tadashi Miyakawa; Ryu Ogiwara; Ryo Fukuda; Ryosuke Takizawa; Kosuke Hatsuda; Fumiyoshi Matsuoka; Yasushi Nagadomi; Daisuke Hashimoto; et al. (ISSCC, 2009)

A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM. - Daisaburo Takashima; Hidehiro Shiga; Daisuke Hashimoto; Tadashi Miyakawa; Shinichiro Shiratake; Katsuhiko Hoya; Ryu Ogiwara; Ryosuke Takizawa; Ryosuke Doumae; Ryo Fukuda; Yohji Watanabe; Shuso Fujii; et al. (ISSCC, 2010)

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes. - Hidehiro Shiga; Daisaburo Takashima; Shinichiro Shiratake; Katsuhiko Hoya; Tadashi Miyakawa; Ryu Ogiwara; Ryo Fukuda; Ryosuke Takizawa; Kosuke Hatsuda; Fumiyoshi Matsuoka; Yasushi Nagadomi; Daisuke Hashimoto; et al. (IEEE J. Solid State Circuits, 2010)

A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs. - Daisaburo Takashima; Hidehiro Shiga; Daisuke Hashimoto; Tadashi Miyakawa; Shinichiro Shiratake; Katsuhiko Hoya; Ryu Ogiwara; Ryosuke Takizawa; Ryosuke Doumae; Ryo Fukuda; Yohji Watanabe; Shuso Fujii; et al. (IEEE J. Solid State Circuits, 2011)

Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs. - Ryu Ogiwara; Daisaburo Takashima; Sumiko M. Doumae; Shinichiro Shiratake; Ryosuke Takizawa; Hidehiro Shiga (IEEE J. Solid State Circuits, 2015)

30.6 A 64Gb DDR4 STT-MRAM Using a Time-Controlled Discharge-Reading Scheme for a .001681µm 1T-1MTJ Cross-Point Cell. - Kosuke Hatsuda; Katsuhiko Hoya; Ryosuke Takizawa; Fumiyoshi Matsuoka; Takaya Yasuda; Akira Katayama; Tadashi Miyakawa; Kazuyo Senju; Kazuki Okawa; Yuka Furukawa; Yu Shimada; Katsuya Kotake; et al. (ISSCC, 2025)