A 300-MPOS video signal processor with a parallel architecture. - Toshihiro Minami; Ryota Kasai; Hironori Yamauchi; Yutaka Tashiro; Jun-ichi Takahashi; Shigeru Date (IEEE J. Solid State Circuits, 1991)

A Hardware/Software Concurrent Design for a Real-Time SP@ML MPEG2 Video-Encoder Chip Set. - Mitsuo Ikeda; Tsuneo Okubo; Tetsuya Abe; Yoshinori Ito; Yutaka Tashiro; Ryota Kasai (ED&TC, 1996)

A real-time motion estimation and compensation LSI with wide search range for MPEG2 video encoding. - Kazuhito Suguri; Toshihiro Minami; Hiroaki Matsuda; Ritsu Kusaba; Toshio Kondo; Ryota Kasai; Takumi Watanabe; Hidenuri Sato; Nobutarou Shibata; Yutaka Tashiro; Takaaki Izuoka; Atsushi Shimizu; et al. (IEEE J. Solid State Circuits, 1996)

Two-chip MPEG-2 video encoder. - Toshio Kondo; Kazuhito Suguri; Mitsuo Ikeda; Tetsuya Abe; Hiroaki Matsuda; Tsuneo Okubo; Kenji Ogura; Yutaka Tashiro; Naoki Ono; Toshihiro Minami; Ritsu Kusaba; Takeshi Ikenaga; et al. (IEEE Micro, 1996)

SuperENC: MPEG-2 video encoder chip. - Mitsuo Ikeda; Toshio Kondo; Koyo Nitta; Kazuhito Suguri; Takeshi Yoshitome; Toshihiro Minami; Hiroe Iwasaki; Katsuyuki Ochiai; Jiro Naganuma; Makoto Endo; Yutaka Tashiro; Hiroshi Watanabe 005; et al. (IEEE Micro, 1999)

Concurrent and collaborative methodologies in short TAT LSI design and manufacturing. - Tsuneo Okubo; Mitsuo Ikeda; Yutaka Tashiro; Toshio Kondo; Ryota Kasai; Hiroshi Kotera; Tetsuma Sakurai (Syst. Comput. Jpn., 1999)