Base Address Recognition with Data Flow Tracking for Injection Attack Detection. - Satoshi Katsunuma; Hiroyuki Kurita; Ryota Shioya; Kazuto Shimizu; Hidetsugu Irie; Masahiro Goshima; Shuichi Sakai (PRDC, 2006)

String-Wise Information Flow Tracking against Script Injection Attacks. - Kunbo Li; Ryota Shioya; Masahiro Goshima; Shuichi Sakai (PRDC, 2009)

Register Cache System Not for Latency Reduction Purpose. - Ryota Shioya; Kazuo Horio; Masahiro Goshima; Shuichi Sakai (MICRO, 2010)

Low-Overhead Architecture for Security Tag. - Ryota Shioya; Daewung Kim; Kazuo Horio; Masahiro Goshima; Shuichi Sakai (IEICE Trans. Inf. Syst., 2011)

Register Indirect Jump Target Forwarding. - Ryota Shioya; Naruki Kurata; Takashi Toyoshima; Masahiro Goshima; Shuichi Sakai (IEICE Trans. Inf. Syst., 2013)

Energy efficiency improvement of renamed trace cache through the reduction of dependent path length. - Ryota Shioya; Hideki Ando (ICCD, 2014)

A Front-End Execution Architecture for High Energy Efficiency. - Ryota Shioya; Masahiro Goshima; Hideki Ando (MICRO, 2014)

Address Order Violation Detection with Parallel Counting Bloom Filters. - Naruki Kurata; Ryota Shioya; Masahiro Goshima; Shuichi Sakai (IEICE Trans. Electron., 2015)

Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control. - Hideki Ando; Ryota Shioya (IEICE Trans. Inf. Syst., 2016)

Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency. - Ryota Shioya; Hideki Ando (IEICE Trans. Inf. Syst., 2016)

FXA: Executing Instructions in Front-End for Energy Efficiency. - Ryota Shioya; Ryo Takami; Masahiro Goshima; Hideki Ando (IEICE Trans. Inf. Syst., 2016)

Initial study of a phase-aware scheduling for hardware transactional memory. - Tomoki Tajimi; Anju Hirota; Ryota Shioya; Masahiro Goshima; Tomoaki Tsumura (PACRIM, 2017)

Applying Razor Flip-Flops to SRAM Read Circuits. - Ushio Jimbo; Junji Yamada; Ryota Shioya; Masahiro Goshima (IEICE Trans. Electron., 2017)

Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology. - Junji Yamada; Ushio Jimbo; Ryota Shioya; Masahiro Goshima; Shuichi Sakai (IEICE Trans. Electron., 2017)

Skewed Multistaged Multibanked Register File for Area and Energy Efficiency. - Junji Yamada; Ushio Jimbo; Ryota Shioya; Masahiro Goshima; Shuichi Sakai (IEICE Trans. Inf. Syst., 2017)

A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode. - Yasumasa Chidai; Kojiro Izuoka; Ryota Shioya; Masahiro Goshima; Hideki Ando (ARCS, 2018)

An Area-Efficient Out-of-Order Soft-Core Processor Without Register Renaming. - Junichiro Kadomoto; Toru Koizumi 001; Akifumi Fukuda; Reoma Matsuo; Susumu Mashimo; Akifumi Fujita; Ryota Shioya; Hidetsugu Irie; Shuichi Sakai (FPT, 2018)

Application of Timing Fault Detection to Rocket Core on FPGA. - Ushio Jimbo; Ryota Shioya; Masahiro Goshima (CANDAR Workshops, 2018)

Rearranging Random Issue Queue with High IPC and Short Delay. - Shinji Sakai; Taishi Suenaga; Ryota Shioya; Hideki Ando (ICCD, 2018)

An Analysis and a Solution of False Conflicts for Hardware Transactional Memory. - Yuki Futamase; Masaki Hayashi; Tomoki Tajimi; Ryota Shioya; Masahiro Goshima; Tomoaki Tsumura (ICECS, 2018)

Isolation-Safe Speculative Access Control for Hardware Transactional Memory. - Tomoki Tajimi; Masaki Hayashi; Yuki Futamase; Ryota Shioya; Masahiro Goshima; Tomoaki Tsumura (ICECS, 2018)

STRAIGHT: Hazardless Processor Architecture Without Register Renaming. - Hidetsugu Irie; Toru Koizumi 001; Akifumi Fukuda; Seiya Akaki; Satoshi Nakae; Yutaro Bessho; Ryota Shioya; Takahiro Notsu; Katsuhiro Yoda; Teruo Ishihara; Shuichi Sakai (MICRO, 2018)

VMOR: Microarchitectural Support for Operand Access in an Interpreter. - Susumu Mashimo; Ryota Shioya; Koji Inoue (IEEE Comput. Archit. Lett., 2018)

Performance Improvement Techniques in Tightly Coupled Multicore Architectures for Single-Thread Applications. - Keita Doi; Ryota Shioya; Hideki Ando (J. Inf. Process., 2018)

Bank-Aware Instruction Scheduler for a Multibanked Register File. - Junji Yamada; Ushio Jimbo; Ryota Shioya; Masahiro Goshima; Shuichi Sakai (J. Inf. Process., 2018)

An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor. - Susumu Mashimo; Koji Inoue; Ryota Shioya; Akifumi Fujita; Reoma Matsuo; Seiya Akaki; Akifumi Fukuda; Toru Koizumi 001; Junichiro Kadomoto; Hidetsugu Irie; Masahiro Goshima (FPT, 2019)

Improving the Instruction Fetch Throughput with Dynamically Configuring the Fetch Pipeline. - Reoma Matsuo; Ryota Shioya; Hideki Ando (IEEE Comput. Archit. Lett., 2019)

A High-Performance Out-of-Order Soft Processor Without Register Renaming. - Satoshi Mitsuno; Junichiro Kadomoto; Toru Koizumi 001; Ryota Shioya; Hidetsugu Irie; Shuichi Sakai (FPL, 2020)

Energy Efficient Runahead Execution on a Tightly Coupled Heterogeneous Core. - Susumu Mashimo; Ryota Shioya; Koji Inoue (HPC Asia, 2020)

Compiling and Optimizing Real-world Programs for STRAIGHT ISA. - Toru Koizumi 001; Shu Sugita; Ryota Shioya; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (ICCD, 2021)

Accurate and Fast Performance Modeling of Processors with Decoupled Front-end. - Yuya Degawa; Toru Koizumi 001; Tomoki Nakamura; Ryota Shioya; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (ICCD, 2021)

The Granularity Gap Problem: A Hurdle for Applying Approximate Memory to Complex Data Layout. - Soramichi Akiyama; Ryota Shioya (ICPE, 2021)

T-SKID: Predicting When to Prefetch Separately from Address Prediction. - Toru Koizumi 001; Tomoki Nakamura; Yuya Degawa; Hidetsugu Irie; Shuichi Sakai; Ryota Shioya (DATE, 2022)

Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag Comparison. - Yasutaka Matsuda; Ryota Shioya; Hideki Ando (IEICE Trans. Inf. Syst., 2022)

CNFET7: An Open Source Cell Library for 7-nm CNFET Technology. - Chenlin Shi; Shinobu Miwa; Tongxin Yang; Ryota Shioya; Hayato Yamaki; Hiroki Honda (ASP-DAC, 2023)

A Sound and Complete Algorithm for Code Generation in Distance-Based ISA. - Shu Sugita; Toru Koizumi 001; Ryota Shioya; Hidetsugu Irie; Shuichi Sakai (CC, 2023)

Out-of-Step Pipeline for Gather/Scatter Instructions. - Yi Ge; Katsuhiro Yoda; Makiko Ito; Toshiyuki Ichiba; Takahide Yoshikawa; Ryota Shioya; Masahiro Goshima (DATE, 2023)

SurgeFuzz: Surge-Aware Directed Fuzzing for CPU Designs. - Yuichi Sugiyama; Reoma Matsuo; Ryota Shioya (ICCAD, 2023)

An Out-of-Order Superscalar Processor Using STRAIGHT Architecture in 28 nm CMOS. - Taichi Amano; Junichiro Kadomoto; Satoshi Mitsuno; Toru Koizumi 001; Ryota Shioya; Hidetsugu Irie; Shuichi Sakai (ISCAS, 2023)

Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors. - Toru Koizumi 001; Ryota Shioya; Shu Sugita; Taichi Amano; Yuya Degawa; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (MICRO, 2023)

PEZY-SC3: A MIMD Many-core Processor for Energy-efficient Computing. - Naoya Hatta; Shuntaro Tsunoda; Kouhei Uchida; Taichi Ishitani; Ryota Shioya; Kei Ishii (CoRR, 2023)

Collecting Cyclic Garbage across Foreign Function Interfaces: Who Takes the Last Piece of Cake? - Tetsuro Yamazaki; Tomoki Nakamaru; Ryota Shioya; Tomoharu Ugawa; Shigeru Chiba (Proc. ACM Program. Lang., 2023)

A Principal Factor of Performance in Decoupled Front-End. - Yuya Degawa; Toru Koizumi 001; Tomoki Nakamura; Ryota Shioya; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (IEICE Trans. Inf. Syst., 2023)

Branch Divergence-Aware Flexible Approximating Technique on GPUs. - Reoma Matsuo; Yuya Degawa; Hidetsugu Irie; Shuichi Sakai; Ryota Shioya (COOL CHIPS, 2024)

ReOVE: Restricted Out-of-Order Execution for Superscalar Processors with Vector Extension. - Masayuki Kimura; Ryota Shioya (ISLPED, 2024)

Error Distribution Estimation for Fixed-point Arithmetic using Program Derivatives. - Soramichi Akiyama; Ryota Shioya; Yuto Miyatake; Tongxin Yang (ISQED, 2024)

Dynamic Possible Source Count Analysis for Data Leakage Prevention. - Eri Ogawa; Tetsuro Yamazaki; Ryota Shioya (MPLR, 2024)

Dynamic Controllability Analysis for Preventing Injection Attacks. - Eri Ogawa; Tetsuro Yamazaki; Ryota Shioya (PRDC, 2024)

CNFET-OCL: Open-Source Cell Libraries for Advanced CNFET Technologies. - Chenlin Shi; Shinobu Miwa; Tongxin Yang; Ryota Shioya; Hayato Yamaki; Hiroki Honda (IEEE Access, 2024)

TURBULENCE: Complexity-Effective Out-of-Order Execution on GPU With Distance-Based ISA. - Reoma Matsuo; Toru Koizumi 001; Hidetsugu Irie; Shuichi Sakai; Ryota Shioya (IEEE Comput. Archit. Lett., 2024)

Veryl: A New Hardware Description Language as an Altarnative to SystemVerilog. - Naoya Hatta; Taichi Ishitani; Ryota Shioya (CoRR, 2024)

Trailing-Ones Anticipation for Reducing the Latency of the Rounding Incrementer in FP FMA Units. - Toru Koizumi 001; Ryota Shioya; Takuya Yamauchi; Tomoya Adachi; Ken Namura; Jun Makino (ARITH, 2025)

CACTI-CNFET: an Analytical Tool for Timing, Power, and Area of SRAMs with Carbon Nanotube Field Effect Transistors. - Shinobu Miwa; Eiichiro Sekikawa; Tongxin Yang; Ryota Shioya; Hayato Yamaki; Hiroki Honda (ASP-DAC, 2025)

Biotite: A High-Performance Static Binary Translator using Source-Level Information. - Changbin Chen; Shu Sugita; Yotaro Nada; Hidetsugu Irie; Shuichi Sakai; Ryota Shioya (CC, 2025)

AceCov: Auxiliary Composite Edge Coverage for Fuzzing. - Haruki Yoshida; Yuichi Sugiyama; Ryota Shioya (EuroS&P, 2025)

Enhancing GPU Performance Through Complexity-Effective Out-of-Order Execution Using Distance-Based ISA. - Reoma Matsuo; Toru Koizumi 001; Hidetsugu Irie; Shuichi Sakai; Ryota Shioya (IEICE Trans. Inf. Syst., 2025)

Flexible Approximate Computing for Mitigating Branch Divergence in GPUs. - Reoma Matsuo; Yuya Degawa; Hidetsugu Irie; Shuichi Sakai; Ryota Shioya (IEEE Micro, 2025)