A low power NoC router using the marching memory through type. - Ryota Yasudo; Takahiro Kagami; Hideharu Amano; Yasunobu Nakase; Masashi Watanabe; Tsukasa Oishi; Toru Shimizu; Tadao Nakamura (COOL Chips, 2014)

Design of a low power NoC router using Marching Memory Through type. - Ryota Yasudo; Takahiro Kagami; Hideharu Amano; Yasunobu Nakase; Masashi Watanabe; Tsukasa Oishi; Toru Shimizu; Tadao Nakamura (NOCS, 2014)

On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck. - Ryota Yasudo; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano; Tadao Nakamura (NOCS, 2015)

HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies. - Ryuta Kawano; Ryota Yasudo; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (ICPADS, 2017)

Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks. - Ryota Yasudo; Michihiro Koibuchi; Koji Nakano; Hiroki Matsutani; Hideharu Amano (ICPP, 2017)

3D Layout of Spidergon, Flattened Butterfly and Dragonfly on a Chip Stack with Inductive Coupling Through Chip Interface. - Hiroshi Nakahara; Ryota Yasudo; Hiroki Matsutani; Hideharu Amano; Michihiro Koibuchi (ISPAN-FCST-ISCC, 2017)

XYZ-Randomization using TSVs for Low-Latency Energy Efficient 3D-NoCs. - Hiroshi Nakahara; Ng. Anh Vu Doan; Ryota Yasudo; Hideharu Amano (NOCS, 2017)

Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers. - Ryota Yasudo; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano; Tadao Nakamura (IEEE Trans. Computers, 2017)

Performance Prediction for Large-Scale Heterogeneous Platforms. - Ryota Yasudo; Ana Lucia Varbanescu; José Gabriel F. Coutinho; Wayne Luk; Hideharu Amano (FCCM, 2018)

Performance Estimation for Exascale Reconfigurable Dataflow Platforms. - Ryota Yasudo; José Gabriel F. Coutinho; Ana Lucia Varbanescu; Wayne Luk; Hideharu Amano; Tobias Becker (FPT, 2018)

k-Optimized Path Routing for High-Throughput Data Center Networks. - Ryuta Kawano; Ryota Yasudo; Hiroki Matsutani; Hideharu Amano (CANDAR, 2018)

Folded Bloom Filter for High Bandwidth Memory, with GPU Implementations. - Masatoshi Hayashikawa; Koji Nakano; Yasuaki Ito; Ryota Yasudo (CANDAR, 2019)

The Degree Diameter Problem for Host-Switch Graphs. - Ryota Yasudo; Koji Nakano (CANDAR Workshops, 2019)

Designing High-Performance Interconnection Networks with Host-Switch Graphs. - Ryota Yasudo; Michihiro Koibuchi; Koji Nakano; Hiroki Matsutani; Hideharu Amano (IEEE Trans. Parallel Distributed Syst., 2019)

Dual-Plane Isomorphic Hypercube Network. - Takeo Hosomi; Ryota Yasudo; Michihiro Koibuchi; Shinji Shimojo (HPC Asia, 2020)

Efficient GPU Implementation for Solving the Maximum Independent Set Problem. - Tomohiro Imanaga; Koji Nakano; Masaki Tao; Ryota Yasudo; Yasuaki Ito; Yuya Kawamata; Ryota Katsuki; Yusuke Tabata; Takashi Yazane; Kenichiro Hamano (CANDAR, 2020)

Fully-Pipelined Architecture for Simulated Annealing-based QUBO Solver on the FPGA. - Hiroshi Kagawa; Yasuaki Ito; Koji Nakano; Ryota Yasudo; Yuya Kawamata; Ryota Katsuki; Yusuke Tabata; Takashi Yazane; Kenichiro Hamano (CANDAR, 2020)

Adaptive Bulk Search: Solving Quadratic Unconstrained Binary Optimization Problems on Multiple GPUs. - Ryota Yasudo; Koji Nakano; Yasuaki Ito; Masaru Tatekawa; Ryota Katsuki; Takashi Yazane; Yoko Inaba (ICPP, 2020)

A Work-Time Optimal Parallel Exhaustive Search Algorithm for the QUBO and the Ising model, with GPU implementation. - Masaki Tao; Koji Nakano; Yasuaki Ito; Ryota Yasudo; Masaru Tatekawa; Ryota Katsuki; Takashi Yazane; Yoko Inaba (IPDPS Workshops, 2020)

A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks. - Ryuta Kawano; Ryota Yasudo; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (IEICE Trans. Inf. Syst., 2020)

Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks. - Ryuta Kawano; Ryota Yasudo; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (IEICE Trans. Inf. Syst., 2020)

Solving the sparse QUBO on multiple GPUs for Simulating a Quantum Annealer. - Tomohiro Imanaga; Koji Nakano; Ryota Yasudo; Yasuaki Ito; Yuya Kawamata; Ryota Katsuki; Shiro Ozaki; Takashi Yazane; Kenichiro Hamano (CANDAR, 2021)

Efficient implementations of Bloom filter using block RAMs and DSP slices on the FPGA. - Takuma Wada; Naoki Matsumura; Ryota Yasudo; Koji Nakano; Yasuaki Ito (Concurr. Comput. Pract. Exp., 2021)

Analytical Performance Estimation for Large-Scale Reconfigurable Dataflow Platforms. - Ryota Yasudo; José Gabriel de Figueiredo Coutinho; Ana Lucia Varbanescu; Wayne Luk; Hideharu Amano; Tobias Becker; Ce Guo (ACM Trans. Reconfigurable Technol. Syst., 2021)

Optimizing Application Mapping for Multi-FPGA Systems with Multi-ejection STDM Switches. - Kohei Ito; Ryota Yasudo; Hideharu Amano (FPL, 2022)

Elastic Sample Filter: An FPGA-based Accelerator for Bayesian Network Structure Learning. - Ryota Miyagi; Ryota Yasudo; Kentaro Sano; Hideki Takase (FPT, 2022)

Graph-theoretic Formulation of QUBO for Scalable Local Search on GPUs. - Ryota Yasudo; Koji Nakano; Yasuaki Ito; Yuya Kawamata; Ryota Katsuki; Shiro Ozaki; Takashi Yazane; Kenichiro Hamano (IPDPS Workshops, 2022)

GPU-accelerated scalable solver with bit permutated cyclic-min algorithm for quadratic unconstrained binary optimization. - Ryota Yasudo; Koji Nakano; Yasuaki Ito; Ryota Katsuki; Yusuke Tabata; Takashi Yazane; Kenichiro Hamano (J. Parallel Distributed Comput., 2022)

Dual Diagonal Mesh: An Optimal Memory Cube Network Under Geometric Constraints. - Masashi Oda; Kai Keida; Ryota Yasudo (candar, 2023)

Performance Modeling and Scalability Analysis of Stream Computing in ESSPER FPGA Clusters. - Ryota Miyagi; Ryota Yasudo; Kentaro Sano; Hideki Takase (ICFPT, 2023)

Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension. - Kazushi Kawamura; Jaehoon Yu; Daiki Okonogi; Satoru Jimbo; Genta Inoue; Akira Hyodo; Ángel López García-Arias; Kota Ando; Bruno Hideki Fukushima-Kimura; Ryota Yasudo; Thiem Van Chu; Masato Motomura (ISSCC, 2023)

Bandit-based Variable Fixing for Binary Optimization on GPU Parallel Computing. - Ryota Yasudo (PDP, 2023)

Simple iterative trial search for the maximum independent set problem optimized for the GPUs. - Tomohiro Imanaga; Koji Nakano; Ryota Yasudo; Yasuaki Ito; Yuya Kawamata; Ryota Katsuki; Yusuke Tabata; Takashi Yazane; Kenichiro Hamano (Concurr. Comput. Pract. Exp., 2023)

High-throughput FPGA implementation for quadratic unconstrained binary optimization. - Hiroshi Kagawa; Yasuaki Ito; Koji Nakano; Ryota Yasudo; Yuya Kawamata; Ryota Katsuki; Yusuke Tabata; Takashi Yazane; Kenichiro Hamano (Concurr. Comput. Pract. Exp., 2023)

Designing low-diameter interconnection networks with multi-ported host-switch graphs. - Ryota Yasudo; Koji Nakano; Michihiro Koibuchi; Hiroki Matsutani; Hideharu Amano (Concurr. Comput. Pract. Exp., 2023)

Solving the QAP by Two-Stage Graph Pointer Networks and Reinforcement Learning. - Satoko Iida; Ryota Yasudo (CoRR, 2024)

Power Optimized Design Framework for FPGA Clusters. - Kensuke Iizuka; Kohei Ito; Ryota Yasudo; Hideharu Amano (IPSJ Trans. Syst. LSI Des. Methodol., 2024)

A low-latency memory-cube network with dual diagonal mesh topology and bypassed pipelines. - Masashi Oda; Kai Keida; Ryota Yasudo (Concurr. Comput. Pract. Exp., 2024)

Trustworthy Deep Learning Acceleration with Customizable Design Flow Automation. - Zhiqiang Que; Hongxiang Fan; Gabriel F. Figueiredo; Ce Guo; Wayne Luk; Ryota Yasudo; Masato Motomura (HEART, 2025)

RL-assisted Annealing for QUBO on a Multi-GPU System. - Reo Gakumi; Ryota Yasudo (IPDPS (Workshops), 2025)

A Scalable Accelerator for Local Score Computation of Structure Learning in Bayesian Networks. - Ryota Miyagi; Ryota Yasudo; Kentaro Sano; Hideki Takase (ACM Trans. Reconfigurable Technol. Syst., 2025)