A low local input 1.9 GHz Si-bipolar quadrature modulator with no adjustment. - Shoji Otaka; Takafumi Yamaji; Ryuichi Fujimoto; Chikau Takahashi; Hiroshi Tanimoto (IEEE J. Solid State Circuits, 1996)

A 2.7-V, 200-kHz, 49-dBm, stopband-IIP3, low-noise, fully balanced gm-C filter IC. - Tetsuro Itakura; Takashi Ueno; Hiroshi Tanimoto; Akira Yasuda; Ryuichi Fujimoto; Tadashi Arai; Hideyuki Kokatsu (IEEE J. Solid State Circuits, 1999)

A 7-GHz 1.8-dB NF CMOS low-noise amplifier. - Ryuichi Fujimoto; Kenji Kojima; Shoji Otaka (IEEE J. Solid State Circuits, 2002)

A Low LO Leakage and Low Power LO Buffer for Direct-Conversion Quadrature Demodulator. - Toshiya Mitomo; Osamu Watanabe 003; Shoji Otaka; Ryuichi Fujimoto; Shunji Kawaguchi (IEICE Trans. Electron., 2005)

A Direct Conversion Receiver for W-CDMA Reducing Current Consumption to 31 mA. - Hiroshi Yoshida; Takehiko Toyoda; Makoto Arai; Ryuichi Fujimoto; Toshiya Mitomo; Masato Ishii; Rui Ito; Tadashi Arai; Tetsuro Itakura; Hiroshi Tsurumi (IEICE Trans. Electron., 2005)

A 60-GHz phase-locked loop with inductor-less prescaler in 90-nm CMOS. - Hiroaki Hoshino; Ryoichi Tachibana; Toshiya Mitomo; Naoko Ono; Yoshiaki Yoshihara; Ryuichi Fujimoto (ESSCIRC, 2007)

A Quadrature Demodulator for WCDMA Receiver Using Common-Base Input Stage with Robustness to Transmitter Leakage. - Toshiya Mitomo; Osamu Watanabe 003; Ryuichi Fujimoto; Shunji Kawaguchi (IEICE Trans. Electron., 2007)

A Low-Noise Amplifier for WCDMA Terminal with High Tolerance for Leakage Signal from Transmitter. - Ryuichi Fujimoto; Gaku Takemura; Masato Ishii; Takehiko Toyoda; Hiroshi Tsurumi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

A 60-GHz CMOS Receiver Front-End With Frequency Synthesizer. - Toshiya Mitomo; Ryuichi Fujimoto; Naoko Ono; Ryoichi Tachibana; Hiroaki Hoshino; Yoshiaki Yoshihara; Yukako Tsutsumi; Ichiro Seto (IEEE J. Solid State Circuits, 2008)

A single-chip RF tuner / OFDM demodulator for mobile digital TV application. - Tsuyoshi Sekine; Ryuichi Fujimoto; Yoshimitsu Takamatsu; Mitsumasa Nakamura; Takuya Hirakawa; Masato Ishii; Takaya Yasuda; Motohiko Hayashi; H. Itoh; Yoko Wada; Teruo Imayama; Tatsuro Oomoto; et al. (ESSCIRC, 2009)

A 60-GHz Phase-Locked Loop with Inductor-Less Wide Operation Range Prescaler in 90-nm CMOS. - Hiroaki Hoshino; Ryoichi Tachibana; Toshiya Mitomo; Naoko Ono; Yoshiaki Yoshihara; Ryuichi Fujimoto (IEICE Trans. Electron., 2009)

140GHz CMOS amplifier with group delay variation of 10.2ps and 0.1dB bandwidth of 12GHz. - Mizuki Motoyoshi; Ryuichi Fujimoto; Kyoya Takano; Minoru Fujishima (IEICE Electron. Express, 2011)

Device Modeling Techniques for High-Frequency Circuits Design Using Bond-Based Design at over 100 GHz. - Ryuichi Fujimoto; Kyoya Takano; Mizuki Motoyoshi; Uroschanit Yodprasit; Minoru Fujishima (IEICE Trans. Electron., 2011)

A Single-Chip RF Tuner/OFDM Demodulator for Mobile Digital TV Application. - Yoshimitsu Takamatsu; Ryuichi Fujimoto; Tsuyoshi Sekine; Takaya Yasuda; Mitsumasa Nakamura; Takuya Hirakawa; Masato Ishii; Motohiko Hayashi; Hiroya Ito; Yoko Wada; Teruo Imayama; Tatsuro Oomoto; et al. (IEICE Trans. Electron., 2011)

Analysis of De-Embedding Error Cancellation in Cascade Circuit Design. - Kyoya Takano; Ryuichi Fujimoto; Kosuke Katayama; Mizuki Motoyoshi; Minoru Fujishima (IEICE Trans. Electron., 2011)

A -70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS. - Daisuke Miyashita; Kenichi Agawa; Hirotsugu Kajihara; Kenichi Sami; Masaomi Iwanaga; Yosuke Ogasawara; Tomohiko Ito; Daisuke Kurose; Naotaka Koide; Toru Hashimoto; Hiroki Sakurai; Takafumi Yamaji; et al. (VLSIC, 2012)

135 GHz 98 mW 10 Gbps ASK transmitter and receiver chipset in 40 nm CMOS. - Naoko Ono; Mizuki Motoyoshi; Kyoya Takano; Kosuke Katayama; Ryuichi Fujimoto; Minoru Fujishima (VLSIC, 2012)

A 120-GHz Transmitter and Receiver Chipset with 9-Gbps Data Rate Using 65-nm CMOS Technology. - Ryuichi Fujimoto; Mizuki Motoyoshi; Kyoya Takano; Uroschanit Yodprasit; Minoru Fujishima (IEICE Trans. Electron., 2012)

Bias-Voltage-Dependent Subcircuit Model for Millimeter-Wave CMOS Circuit. - Kosuke Katayama; Mizuki Motoyoshi; Kyoya Takano; Ryuichi Fujimoto; Minoru Fujishima (IEICE Trans. Electron., 2012)

A-104 dBc/Hz In-Band Phase Noise 3 GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter. - Daisuke Miyashita; Hiroyuki Kobayashi; Jun Deguchi; Shouhei Kousai; Mototsugu Hamada; Ryuichi Fujimoto (IEICE Trans. Electron., 2012)

14.4mW 10Gbps CMOS limiting amplifier with local DC offset cancellers. - Kyoya Takano; Ryuichi Fujimoto; Mizuki Motoyoshi; Kosuke Katayama; Minoru Fujishima (RWS, 2013)

Foreword. - Ryuichi Fujimoto (IEICE Trans. Electron., 2013)

A 120 GHz/140 GHz Dual-Channel OOK Receiver Using 65 nm CMOS Technology. - Ryuichi Fujimoto; Mizuki Motoyoshi; Kyoya Takano; Minoru Fujishima (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

A -70 dBm-Sensitivity 522 Mbps 0.19 nJ/bit-TX 0.43 nJ/bit-RX Transceiver for TransferJetTM SoC in 65 nm CMOS. - Daisuke Miyashita; Kenichi Agawa; Hirotsugu Kajihara; Kenichi Sami; Ichiro Seto; Ryuichi Fujimoto; Yasuo Unekawa (IEICE Trans. Electron., 2013)

98 mW 10 Gbps Wireless Transceiver Chipset With D-Band CMOS Circuits. - Minoru Fujishima; Mizuki Motoyoshi; Kosuke Katayama; Kyoya Takano; Naoko Ono; Ryuichi Fujimoto (IEEE J. Solid State Circuits, 2013)

A 0.171-mW, 2.4-GHz Class-D VCO with dynamic supply voltage control. - Yoshiaki Yoshihara; Hideaki Majima; Ryuichi Fujimoto (ESSCIRC, 2014)

3D-integrated, low-height, small module design techniques for 4.48GHz, 560MHz-bandwidth TransferJet™ transceiver. - Kenichi Agawa; Ichiro Seto; Akihiko Happoya; Yoshihiro Iida; Yusuke Imaizumi; Motochika Okano; Daigo Suzuki; Yuichi Sato; Masaomi Iwanaga; Kazumi Sato; Satoshi Arai; Noriaki Uchida; et al. (RWS, 2014)

All-digital single-inductor multiple-output DC-DC converter with over 65.3% efficiency in 1 uW to 50 mW load range and 86.3% peak efficiency. - Manabu Yamada; Nam Binh Tran; Takayuki Miyazaki; Yoshiaki Yoshihara; Ryuichi Fujimoto (A-SSCC, 2016)

Age estimation using effective brain local features from T1-weighted images. - Ryuichi Fujimoto; Chihiro Kondo; Koichi Ito 001; Kai Wu 002; Kazunori Sato; Yasuyuki Taki; Hiroshi Fukuda; Takafumi Aoki (EMBC, 2016)

An 18 µW spur canceled clock generator for recovering receiver sensitivity in wireless SoCs. - Yosuke Ogasawara; Hiroki Sakurai; Ryuichi Fujimoto; Kenichi Sami (VLSI Circuits, 2016)

Analog and Digital Collaborative Design Techniques for Wireless SoCs. - Ryuichi Fujimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Brain age estimation from T1-weighted images using effective local features. - Ryuichi Fujimoto; Koichi Ito 001; Kai Wu 002; Kazunori Sato; Yasuyuki Taki; Hiroshi Fukuda; Takafumi Aoki (EMBC, 2017)

A low voltage 0.8V RF receiver in 28nm CMOS for 5GHz WLAN. - Atsushi Shirane; Shusuke Kawai; Hiromitsu Aoyama; Rui Ito; Toshiya Mitomo; Hiroyuki Kobayashi; Hiroshi Yoshida; Hideaki Majima; Ryuichi Fujimoto; Hiroshi Tsurumi (ESSCIRC, 2017)

Age estimation from brain MRI images using deep learning. - Tzu-Wei Huang; Hwann-Tzong Chen; Ryuichi Fujimoto; Koichi Ito 001; Kai Wu 002; Kazunori Sato; Yasuyuki Taki; Hiroshi Fukuda; Takafumi Aoki (ISBI, 2017)

An 18 µW Spur Cancelled Clock Generator for Recovering Receiver Sensitivity in Wireless SoCs. - Yosuke Ogasawara; Ryuichi Fujimoto; Tsuneo Suzuki; Kenichi Sami (IEICE Trans. Electron., 2017)

Performance Evaluation of Age Estimation from T1-Weighted Images Using Brain Local Features and CNN. - Koichi Ito 001; Ryuichi Fujimoto; Tzu-Wei Huang; Hwann-Tzong Chen; Kai Wu 002; Kazunori Sato; Yasuyuki Taki; Hiroshi Fukuda; Takafumi Aoki (EMBC, 2018)

A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems. - Yuta Tsubouchi; Daisuke Miyashita; Takashi Toi; Yuji Satoh; Fumihiko Tachibana; Junji Wadatsumi; Makoto Morimoto; Ryuichi Fujimoto; Jun Deguchi (IEEE J. Solid State Circuits, 2019)

Weight Compression MAC Accelerator for Effective Inference of Deep Learning. - Asuka Maki; Daisuke Miyashita; Shinichi Sasaki; Kengo Nakata; Fumihiko Tachibana; Tomoya Suzuki; Jun Deguchi; Ryuichi Fujimoto (IEICE Trans. Electron., 2020)

Quantization Strategy for Pareto-optimally Low-cost and Accurate CNN. - Kengo Nakata; Daisuke Miyashita; Asuka Maki; Fumihiko Tachibana; Shinichi Sasaki; Jun Deguchi; Ryuichi Fujimoto (AICAS, 2021)

Adaptive Quantization Method for CNN with Computational-Complexity-Aware Regularization. - Kengo Nakata; Daisuke Miyashita; Jun Deguchi; Ryuichi Fujimoto (ISCAS, 2021)

A Noise-Canceling Charge Pump for Area Efficient PLL Design. - Go Urakawa; Hiroyuki Kobayashi; Jun Deguchi; Ryuichi Fujimoto (IEICE Trans. Electron., 2021)

A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems. - Takashi Toi; Junji Wadatsumi; Hiroyuki Kobayashi; Yutaka Shimizu; Yuji Satoh; Makoto Morimoto; Rui Ito; Mitsuyuki Ashida; Yuta Tsubouchi; Mai Nozawa; Go Urakawa; Jun Deguchi; et al. (IEEE J. Solid State Circuits, 2022)

Accelerating CNN Inference with an Adaptive Quantization Method Using Computational Complexity-Aware Regularization. - Kengo Nakata; Daisuke Miyashita; Jun Deguchi; Ryuichi Fujimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2025)