Scaling Up Of Wave Pipelines. - Masa-Aki Fukase; Ryusuke Egawa; Tomoaki Sato; Tadao Nakamura (VLSI Design, 2001)

A Systolic Memory Architecture for Fast Codebook Design based on MMPDCL Algorithm. - Kentaro Sano; Chiaki Takagi; Ryusuke Egawa; Ken-ichi Suzuki; Tadao Nakamura (ITCC (1), 2004)

A power-aware shared cache mechanism based on locality assessment of memory reference for CMPs. - Isao Kotera; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (MEDEA@PACT, 2007)

An on-chip cache design for vector processors. - Akihiro Musa; Yoshiei Sato; Ryusuke Egawa; Hiroyuki Takizawa; Koki Okabe; Hiroaki Kobayashi (MEDEA@PACT, 2007)

First Experiences with NEC SX-9. - Hiroaki Kobayashi; Ryusuke Egawa; Hiroyuki Takizawa; Koki Okabe; Akihiko Musa; Takashi Soga; Yoichi Shimomura (High Performance Computing on Vector Systems, 2008)

Effects of MSHR and Prefetch Mechanisms on an On-Chip Cache of the Vector Architecture. - Akihiro Musa; Yoshiei Sato; Takashi Soga; Ryusuke Egawa; Hiroyuki Takizawa; Koki Okabe; Hiroaki Kobayashi (ISPA, 2008)

A Utility-Based Double Auction Mechanism for Efficient Grid Resource Allocation. - Chainan Satayapiwat; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (ISPA, 2008)

Modeling of cache access behavior based on Zipf's law. - Isao Kotera; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (MEDEA@PACT, 2008)

A shared cache for a chip multi vector processor. - Akihiro Musa; Yoshiei Sato; Takashi Soga; Koki Okabe; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (MEDEA@PACT, 2008)

Evaluation of fine grain 3-D integrated arithmetic units. - Ryusuke Egawa; Jubee Tada; Hiroaki Kobayashi; Gensuke Goto (3DIC, 2009)

3D on-chip memory for the vector architecture. - Yusuke Funaya; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (3DIC, 2009)

Performance tuning and analysis of future vector processors based on the roofline model. - Yoshiei Sato; Ryu-ichi Nagaoka; Akihiro Musa; Ryusuke Egawa; Hiroyuki Takizawa; Koki Okabe; Hiroaki Kobayashi (MEDEA@PACT, 2009)

Performance evaluation of NEC SX-9 using real science and engineering applications. - Takashi Soga; Akihiro Musa; Youichi Shimomura; Ryusuke Egawa; Ken'ichi Itakura; Hiroyuki Takizawa; Koki Okabe; Hiroaki Kobayashi (SC, 2009)

Design and early evaluation of a 3-D die stacked chip multi-vector processor. - Ryusuke Egawa; Yusuke Funaya; Ryu-ichi Nagaoka; Akihiro Musa; Hiroyuki Takizawa; Hiroaki Kobayashi (3DIC, 2010)

Cache partitioning strategies for 3-D stacked vector processors. - Yusuke Funaya; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (3DIC, 2010)

A Load-Forwarding Mechanism for the Vector Architecture in Multimedia Applications. - Ye Gao; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (DSD, 2010)

A Majority-Based Control Scheme for Way-Adaptable Caches. - Masayuki Sato 001; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (Facing the Multicore-Challenge, 2010)

A voting-based working set assessment scheme for dynamic cache resizing mechanisms. - Masayuki Sato 001; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (ICCD, 2010)

A History-Based Job Scheduling Mechanism for the Vector Computing Cloud. - Yoshitomo Murata; Ryusuke Egawa; Manabu Higashida; Hiroaki Kobayashi (SAINT, 2010)

A Fast Ray-Tracing Using Bounding Spheres and Frustum Rays for Dynamic Scene Rendering. - Ken-ichi Suzuki; Yoshiyuki Kaeriyama; Kazuhiko Komatsu; Ryusuke Egawa; Nobuyuki Ohba; Hiroaki Kobayashi (IEICE Trans. Inf. Syst., 2010)

Effects of 3-D stacked vector cache on energy consumption. - Ryusuke Egawa; Yusuke Funaya; Ryu-ichi Nagaoka; Yusuke Endo; Akihiro Musa; Hiroyuki Takizawa; Hiroaki Kobayashi (3DIC, 2011)

A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers. - Jubee Tada; Ryusuke Egawa; Kazushige Kawai; Hiroaki Kobayashi; Gensuke Goto (3DIC, 2011)

A Network Clustering Algorithm for Sybil-Attack Resisting. - Ling Xu; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (IEICE Trans. Inf. Syst., 2011)

Power-Aware Dynamic Cache Partitioning for CMPs. - Isao Kotera; Kenta Abe; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (Trans. High Perform. Embed. Archit. Compil., 2011)

An out-of-order vector processing mechanism for multimedia applications. - Ye Gao; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (Conf. Computing Frontiers, 2012)

A capacity-efficient insertion policy for dynamic cache resizing mechanisms. - Masayuki Sato 001; Yusuke Tobo; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (Conf. Computing Frontiers, 2012)

A media-oriented vector architectural extension with a high bandwidth cache system. - Ye Gao; Naoki Shoji; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (COOL Chips, 2012)

Abstract: Exploring Design Space of a 3D Stacked Vector Cache. - Ryusuke Egawa; Jubee Tada; Yusuke Endo; Hiroyuki Takizawa; Hiroaki Kobayashi (SC Companion, 2012)

Poster: Exploring Design Space of a 3D Stacked Vector Cache - Designing a 3D Stacked Vector Cache using Conventional EDA Tools. - Ryusuke Egawa; Jubee Tada; Yusuke Endo; Hiroyuki Takizawa; Hiroaki Kobayashi (SC Companion, 2012)

Vertically integrated processor and memory module design for vector supercomputers. - Ryusuke Egawa; Masayuki Sato 001; Jubee Tada; Hiroaki Kobayashi (3DIC, 2013)

Design of a 3-D stacked floating-point adder. - Jubee Tada; Ryusuke Egawa; Hiroaki Kobayashi (3DIC, 2013)

A flexible insertion policy for dynamic cache resizing mechanisms. - Masayuki Sato 001; Yusuke Tobo; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (COOL Chips, 2013)

Design and evaluation of a media-oriented vector processor with a multi-banked cache memory. - Ye Gao; Naoki Shoji; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (ESTIMedia, 2013)

A Capacity-Aware Thread Scheduling Method Combined with Cache Partitioning to Reduce Inter-Thread Cache Conflicts. - Masayuki Sato 001; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (IEICE Trans. Inf. Syst., 2013)

On-chip checkpointing with 3D-stacked memories. - Masayuki Sato 001; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (3DIC, 2014)

An impact of circuit scale on the performance of 3-D stacked arithmetic units. - Jubee Tada; Ryusuke Egawa; Hiroaki Kobayashi (3DIC, 2014)

An energy optimization method for vector processing mechanisms. - Ye Gao; Masayuki Sato 001; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (COOL Chips, 2014)

Xevolver: An XML-based code translation framework for supporting HPC application migration. - Hiroyuki Takizawa; Shoichi Hirasawa; Yasuharu Hayashi; Ryusuke Egawa; Hiroaki Kobayashi (HiPC, 2014)

A Compiler-Assisted OpenMP Migration Method Based on Automatic Parallelizing Information. - Kazuhiko Komatsu; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (ISC, 2014)

MVP-Cache: A Multi-Banked Cache Memory for Energy-Efficient Vector Processing of Multimedia Applications. - Ye Gao; Masayuki Sato 001; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (IEICE Trans. Inf. Syst., 2014)

Design of a 3-D stacked floating-point Goldschmidt divider. - Jubee Tada; Ryusuke Egawa; Hiroaki Kobayashi (3DIC, 2015)

An energy-efficient dynamic memory address mapping mechanism. - Masayuki Sato 001; Chengguang Han; Kazuhiko Komatsu; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (COOL Chips, 2015)

Migration of an Atmospheric Simulation Code to an OpenACC Platform Using the Xevolver Framework. - Kazuhiko Komatsu; Ryusuke Egawa; Shoichi Hirasawa; Hiroyuki Takizawa; Ken'ichi Itakura; Hiroaki Kobayashi (CANDAR, 2015)

A Case Study of Memory Optimization for Migration of a Plasmonics Simulation Application to SX-ACE. - Raghunandan Mathur; Hiroshi Matsuoka; Osamu Watanabe; Akihiro Musa; Ryusuke Egawa; Hiroaki Kobayashi (CANDAR, 2015)

FLEXII: A Flexible Insertion Policy for Dynamic Cache Resizing Mechanisms. - Masayuki Sato 001; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (IEICE Trans. Electron., 2015)

A power-aware LLC control mechanism for the 3D-stacked memory system. - Ryusuke Egawa; Wataru Uno; Masayuki Sato 001; Hiroaki Kobayashi; Jubee Tada (3DIC, 2016)

A cache partitioning mechanism to protect shared data for CMPs. - Masayuki Sato 001; Shin Nishimura; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (COOL Chips, 2016)

A Directive Generation Approach Using User-Defined Rules. - Kazuhiko Komatsu; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (CANDAR, 2016)

Translation of Large-Scale Simulation Codes for an OpenACC Platform Using the Xevolver Framework. - Kazuhiko Komatsu; Ryusuke Egawa; Shoichi Hirasawa; Hiroyuki Takizawa; Ken'ichi Itakura; Hiroaki Kobayashi (Int. J. Netw. Comput., 2016)

A Memory-Efficient Implementation of a Plasmonics Simulation Application on SX-ACE. - Raghunandan Mathur; Hiroshi Matsuoka; Osamu Watanabe; Akihiro Musa; Ryusuke Egawa; Hiroaki Kobayashi (Int. J. Netw. Comput., 2016)

Effects of Stacking Granularity on 3-D Stacked Floating-point Fused Multiply Add Units. - Jubee Tada; Maiki Hosokawa; Ryusuke Egawa; Hiroaki Kobayashi (SIGARCH Comput. Archit. News, 2016)

Performance and Power Analysis of SX-ACE Using HP-X Benchmark Programs. - Ryusuke Egawa; Kazuhiko Komatsu; Yoko Isobe; Toshihiro Kato; Souya Fujimoto; Hiroyuki Takizawa; Akihiro Musa; Hiroaki Kobayashi (CLUSTER, 2017)

Vectorization-Aware Loop Optimization with User-Defined Code Transformations. - Hiroyuki Takizawa; Thorsten Reimann; Kazuhiko Komatsu; Takashi Soga; Ryusuke Egawa; Akihiro Musa; Hiroaki Kobayashi (CLUSTER, 2017)

An Adjacent-Line-Merging Writeback Scheme for STT-RAM last-level caches. - Masayuki Sato 001; Zentaro Sakai; Ryusuke Egawa; Hiroaki Kobayashi (COOL Chips, 2017)

An application-adaptive data allocation method for multi-channel memory. - Takuya Toyoshima; Masayuki Sato 001; Ryusuke Egawa; Hiroaki Kobayashi (COOL Chips, 2017)

An Adaptive Demotion Policy for High-Associativity Caches. - Jubee Tada; Masayuki Sato 001; Ryusuke Egawa (HEART, 2017)

A Memory Congestion-Aware MPI Process Placement for Modern NUMA Systems. - Mulya Agung; Muhammad Alfian Amrizal; Kazuhiko Komatsu; Ryusuke Egawa; Hiroyuki Takizawa (HiPC, 2017)

Designing an Open Database of System-Aware Code Optimizations. - Ryusuke Egawa; Kazuhiko Komatsu; Hiroyuki Takizawa (CANDAR, 2017)

An Application-Level Incremental Checkpointing Mechanism with Automatic Parameter Tuning. - Hiroyuki Takizawa; Muhammad Alfian Amrizal; Kazuhiko Komatsu; Ryusuke Egawa (CANDAR, 2017)

A Directive Generation Approach to High Code-Maintainability for Various HPC Systems. - Kazuhiko Komatsu; Ryusuke Egawa; Hiroyuki Takizawa; Hiroaki Kobayashi (Int. J. Netw. Comput., 2017)

Potential of a modern vector supercomputer for practical applications: performance evaluation of SX-ACE. - Ryusuke Egawa; Kazuhiko Komatsu; Shintaro Momose; Yoko Isobe; Akihiro Musa; Hiroyuki Takizawa; Hiroaki Kobayashi (J. Supercomput., 2017)

Automatic Hyperparameter Tuning of Machine Learning Models under Time Constraints. - Zhen Wang; Mulya Agung; Ryusuke Egawa; Reiji Suda; Hiroyuki Takizawa (IEEE BigData, 2018)

A Failure Prediction-Based Adaptive Checkpointing Method with Less Reliance on Temperature Monitoring for HPC Applications. - Muhammad Alfian Amrizal; Pei Li; Mulya Agung; Ryusuke Egawa; Hiroyuki Takizawa (CLUSTER, 2018)

An energy-aware set-level refreshing mechanism for eDRAM last-level caches. - Masayuki Sato 001; Zehua Li; Ryusuke Egawa; Hiroaki Kobayashi (COOL CHIPS, 2018)

Investigating the Effects of Dynamic Thread Team Size Adjustment for Irregular Applications. - Xiong Xiao; Mulya Agung; Muhammad Alfian Amrizal; Ryusuke Egawa; Hiroyuki Takizawa (CANDAR, 2018)

Use of Code Structural Features for Machine Learning to Predict Effective Optimizations. - Yuki Kawarabatake; Mulya Agung; Kazuhiko Komatsu; Ryusuke Egawa; Hiroyuki Takizawa (IPDPS Workshops, 2018)

Risk Management of Heatstroke Based on Fast Computation of Temperature and Water Loss Using Weather Data for Exposure to Ambient Heat and Solar Radiation. - Kazuya Kojima; Akimasa Hirata; Kazuma Hasegawa; Sachiko Kodera; Ilkka Laakso; Daisuke Sasaki; Takeshi Yamashita; Ryusuke Egawa; Yuka Horie; Nanako Yazaki; Saeri Kowata; Kenji Taguchi 002; et al. (IEEE Access, 2018)

An Adjacent-Line-Merging Writeback Scheme for STT-RAM-Based Last-Level Caches. - Masayuki Sato 001; Yoshiki Shoji; Zentaro Sakai; Ryusuke Egawa; Hiroaki Kobayashi (IEEE Trans. Multi Scale Comput. Syst., 2018)

A Design Scheme for 3-D Stacked CNN Accelerators. - Jubee Tada; Kazuto Takahashi; Ryusuke Egawa (3DIC, 2019)

The Impacts of Locality and Memory Congestion-aware Thread Mapping on Energy Consumption of Modern NUMA Systems. - Mulya Agung; Muhammad Alfian Amrizal; Ryusuke Egawa; Hiroyuki Takizawa (COOL CHIPS, 2019)

Performance Improvement of High-Speed File Transfer Over JHPCN. - Praphan Pavarangkoon; Takeshi Nanri; Ken T. Murata; Kazunori Yamamoto; Kazuya Muranaga; Takamichi Mizuhara; Keiichiro Fukazawa; Ryusuke Egawa; Takahiro Katagiri; Masao Ogino (DASC/PiCom/DataCom/CyberSciTech, 2019)

A Layer-Adaptable Cache Hierarchy by a Multiple-layer Bypass Mechanism. - Ryusuke Egawa; Ryoma Saito; Masayuki Sato 001; Hiroaki Kobayashi (HEART, 2019)

An Automatic MPI Process Mapping Method Considering Locality and Memory Congestion on NUMA Systems. - Mulya Agung; Muhammad Alfian Amrizal; Ryusuke Egawa; Hiroyuki Takizawa (MCSoC, 2019)

An OpenCL-Like Offload Programming Framework for SX-Aurora TSUBASA. - Hiroyuki Takizawa; Shinji Shiotsuki; Naoki Ebata; Ryusuke Egawa (PDCAT, 2019)

Peachy Parallel Assignments (EduHPC 2019). - Mulya Agung; Allen D. Malony; Hiroyuki Takizawa; David P. Bunde; Muhammad Alfian Amrizal; Steven Bogaerts; Ryusuke Egawa; Daniel A. Ellsworth; Jorge Fernández-Fabeiro; Arturo González-Escribano; Sukhamay Kundu; Alina Lazar (EduHPC@SC, 2019)

An Energy-aware Dynamic Data Allocation Mechanism for Many-channel Memory Systems. - Masayuki Sato 001; Takuya Toyoshima; Hikaru Takayashiki; Ryusuke Egawa; Hiroaki Kobayashi (Supercomput. Front. Innov., 2019)

Performance Evaluation of Different Implementation Schemes of an Iterative Flow Solver on Modern Vector Machines. - Kenta Yamaguchi; Takashi Soga; Yoichi Shimomura; Thorsten Reimann; Kazuhiko Komatsu; Ryusuke Egawa; Akihiro Musa; Hiroyuki Takizawa; Hiroaki Kobayashi (Supercomput. Front. Innov., 2019)

Polymorphic Data Layout for SX-Aurora TSUBASA Vector Engines. - Naoki Ebata; Yoko Isobe; Ryusuke Egawa; Hiroyuki Takizawa (CANDAR, 2020)

Improving the Accuracy in SpMV Implementation Selection with Machine Learning. - Reo Furuhata; Minglu Zhao; Mulya Agung; Ryusuke Egawa; Hiroyuki Takizawa (CANDAR (Workshops), 2020)

A Conflict-Aware Capacity Control Mechanism for Last-Level Cache. - Jiaheng Liu; Ryusuke Egawa; Mulya Agung; Hiroyuki Takizawa (CANDAR (Workshops), 2020)

Automatically Avoiding Memory Access Conflicts on SX-Aurora TSUBASA. - Naoki Ebata; Ryusuke Egawa; Yoko Isobe; Ryoji Takaki; Hiroyuki Takizawa (IPDPS Workshops, 2020)

Task Priority Control for the HPX Runtime System. - Suhang Jiang; Mulya Agung; Ryusuke Egawa; Hiroyuki Takizawa (IPDPS Workshops, 2020)

Exploiting the Potentials of the Second Generation SX-Aurora TSUBASA. - Ryusuke Egawa; Souya Fujimoto; Tsuyoshi Yamashita; Daisuke Sasaki; Yoko Isobe; Yoichi Shimomura; Hiroyuki Takizawa (PMBS@SC, 2020)

DeLoc: A Locality and Memory-Congestion-Aware Task Mapping Method for Modern NUMA Systems. - Mulya Agung; Muhammad Alfian Amrizal; Ryusuke Egawa; Hiroyuki Takizawa (IEEE Access, 2020)

Xevolver: A code transformation framework for separation of system-awareness from application codes. - Kazuhiko Komatsu; Ayumu Gomi; Ryusuke Egawa; Daisuke Takahashi; Reiji Suda; Hiroyuki Takizawa (Concurr. Comput. Pract. Exp., 2020)

Online MPI Process Mapping for Coordinating Locality and Memory Congestion on NUMA Systems. - Mulya Agung; Muhammad Alfian Amrizal; Ryusuke Egawa; Hiroyuki Takizawa (Supercomput. Front. Innov., 2020)

Effects of Using a Memory Stalled Core for Handling MPI Communication Overlapping in the SOR Solver on SX-ACE and SX-Aurora TSUBASA. - Takashi Soga; Kenta Yamaguchi; Raghunandan Mathur; Osamu Watanabe; Akihiro Musa; Ryusuke Egawa; Hiroaki Kobayashi (Supercomput. Front. Innov., 2020)

Improving Quantum Annealing Performance on Embedded Problems. - Michael R. Zielewski; Mulya Agung; Ryusuke Egawa; Hiroyuki Takizawa (Supercomput. Front. Innov., 2020)

ExaFSA: Parallel Fluid-Structure-Acoustic Simulation. - Florian Lindner; Amin Totounferoush; Miriam Mehl; Benjamin Uekermann; Neda Ebrahimi Pour; Verena Krupp; Sabine Roller; Thorsten Reimann; Dörte C. Sternel; Ryusuke Egawa; Hiroyuki Takizawa; Frédéric Simonis (Software for Exascale Computing, 2020)

Portability of Vectorization-aware Performance Tuning Expertise across System Generations. - Shunpei Sugawara; Yoichi Shimomura; Ryusuke Egawa; Hiroyuki Takizawa (MCSoC, 2021)

Towards Conflict-Aware Workload Co-execution on SX-Aurora TSUBASA. - Riku Nunokawa; Yoichi Shimomura; Mulya Agung; Ryusuke Egawa; Hiroyuki Takizawa (PDCAT, 2021)

Preemptive Parallel Job Scheduling for Heterogeneous Systems Supporting Urgent Computing. - Mulya Agung; Yuta Watanabe; Henning Weber; Ryusuke Egawa; Hiroyuki Takizawa (IEEE Access, 2021)

OpenCL-like offloading with metaprogramming for SX-Aurora TSUBASA. - Hiroyuki Takizawa; Shinji Shiotsuki; Naoki Ebata; Ryusuke Egawa (Parallel Comput., 2021)

Toward Building a Digital Twin of Job Scheduling and Power Management on an HPC System. - Tatsuyoshi Ohmura; Yoichi Shimomura; Ryusuke Egawa; Hiroyuki Takizawa (JSSPP, 2022)

A Partitioned Memory Architecture with Prefetching for Efficient Video Encoders. - Masayuki Sato 001; Yuya Omori; Ryusuke Egawa; Ken Nakamura; Daisuke Kobayashi; Hiroe Iwasaki; Kazuhiko Komatsu; Hiroaki Kobayashi (PDCAT, 2022)

Equivalence Checking of Code Transformation by Numerical and Symbolic Approaches. - Shunpei Sugawara; Keichi Takahashi; Yoichi Shimomura; Ryusuke Egawa; Hiroyuki Takizawa (PDCAT, 2022)

A Conflict-Aware Capacity Control Mechanism for Deep Cache Hierarchy. - Jiaheng Liu; Ryusuke Egawa; Hiroyuki Takizawa (IEICE Trans. Inf. Syst., 2022)

Performance Evaluation of a Next-Generation SX-Aurora TSUBASA Vector Supercomputer. - Keichi Takahashi; Soya Fujimoto; Satoru Nagase; Yoko Isobe; Yoichi Shimomura; Ryusuke Egawa; Hiroyuki Takizawa (ISC, 2023)

A QA-Assisted Job Scheduler for Minimizing the Impact of Urgent Computing on HPC System Operation. - Tatsuyoshi Ohmura; Keichi Takahashi; Ryusuke Egawa; Hiroyuki Takizawa (CANDARW, 2024)

Reuse distance-based shared LLC management mechanism for heterogeneous CPU-GPU systems. - Jiaheng Liu; Ryusuke Egawa; Keichi Takahashi; Yoichi Shimomura; Hiroyuki Takizawa (IEICE Electron. Express, 2024)

Conflict-aware workload co-execution on SX-aurora TSUBASA. - Riku Nunokawa; Yoichi Shimomura; Mulya Agung; Ryusuke Egawa; Hiroyuki Takizawa (CCF Trans. High Perform. Comput., 2024)

Foreword. - Ryusuke Egawa; Yasutaka Wada (IEICE Trans. Electron., 2025)

Special Issue on COOL Chips. - Ryusuke Egawa; Yasutaka Wada (IEEE Micro, 2025)