Optimized Core-Links for Low-Latency NoCs. - Ryuta Kawano; Seiichi Tade; Ikki Fujiwara; Hiroki Matsutani; Hideharu Amano; Michihiro Koibuchi (PDP, 2015)

ACRO: Assignment of channels in reverse order to make arbitrary routing deadlock-free. - Ryuta Kawano; Hiroshi Nakahara; Seiichi Tade; Ikki Fujiwara; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (ICIS, 2016)

Body bias grain size exploration for a coarse grained reconfigurable accelerator. - Yusuke Matsushita 001; Hayate Okuhara; Koichiro Masuyama; Yu Fujita; Ryuta Kawano; Hideharu Amano (FPL, 2016)

LOREN: A Scalable Routing Method for Layout-Conscious Random Topologies. - Ryuta Kawano; Hiroshi Nakahara; Ikki Fujiwara; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (CANDAR, 2016)

HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies. - Ryuta Kawano; Ryota Yasudo; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (ICPADS, 2017)

A Layout-Oriented Routing Method for Low-Latency HPC Networks. - Ryuta Kawano; Hiroshi Nakahara; Ikki Fujiwara; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (IEICE Trans. Inf. Syst., 2017)

A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing. - Ryuta Kawano; Hiroshi Nakahara; Seiichi Tade; Ikki Fujiwara; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (IEICE Trans. Inf. Syst., 2017)

Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator. - Yusuke Matsushita 001; Hayate Okuhara; Koichiro Masuyama; Yu Fujita; Ryuta Kawano; Hideharu Amano (IEICE Trans. Inf. Syst., 2017)

k-Optimized Path Routing for High-Throughput Data Center Networks. - Ryuta Kawano; Ryota Yasudo; Hiroki Matsutani; Hideharu Amano (CANDAR, 2018)

Deadlock-Free Layered Routing for Infiniband Networks. - Ryuta Kawano; Hiroki Matsutani; Hideharu Amano (CANDAR Workshops, 2019)

Layout-Oriented Low-Diameter Topology for HPC Interconnection Networks. - Ryuta Kawano; Hiroki Matsutani; Hideharu Amano (CANDAR (Workshops), 2020)

A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks. - Ryuta Kawano; Ryota Yasudo; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (IEICE Trans. Inf. Syst., 2020)

Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks. - Ryuta Kawano; Ryota Yasudo; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (IEICE Trans. Inf. Syst., 2020)

GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph. - Ryuta Kawano; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (ACIT, 2021)

Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths. - Yoshiya Shikama; Ryuta Kawano; Hiroki Matsutani; Hideharu Amano; Yusuke Nagasaka; Naoto Fukumoto; Michihiro Koibuchi (PDP, 2021)

Dynamic Routing Reconfiguration for Low-Latency and Deadlock-Free Interconnection Networks. - Ryuta Kawano; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (CANDAR, 2022)

A traffic-aware memory-cube network using bypassing. - Yoshiya Shikama; Ryuta Kawano; Hiroki Matsutani; Hideharu Amano; Yusuke Nagasaka; Naoto Fukumoto; Michihiro Koibuchi (Microprocess. Microsystems, 2022)