SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors. - Masanao Yamaoka; Ryuta Tsuchiya; Takayuki Kawahara (IEEE J. Solid State Circuits, 2006)

Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs. - Akira Kotabe; Kiyoo Itoh 001; Riichiro Takemura; Ryuta Tsuchiya; Masashi Horiguchi (CICC, 2011)