A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. - Junshi Hotate; Takashi Kishimoto; Toshiki Higashi; Hiroyuki Ochi; Ryutaro Doi; Munehiro Tada; Tadahiko Sugibayashi; Kazutoshi Wakabayashi; Hidetoshi Onodera; Yukio Mitsuyama; Masanori Hashimoto (FPL, 2016)

Sneak path free reconfiguration of via-switch crossbars based FPGA. - Ryutaro Doi; Jaehoon Yu; Masanori Hashimoto (ICCAD, 2018)

SAT Encoding-Based Verification of Sneak Path Problem in Via-Switch FPGA. - Ryutaro Doi; Masanori Hashimoto (ISVLSI, 2018)

Interconnect Delay Analysis for RRAM Crossbar Based FPGA. - Masanori Hashimoto; Yuki Nakazawa; Ryutaro Doi; Jaehoon Yu (ISVLSI, 2018)

An analytic evaluation on soft error immunity enhancement due to temporal triplication. - Ryutaro Doi; Masanori Hashimoto; Takao Onoye (Int. J. Embed. Syst., 2018)

Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars. - Hiroyuki Ochi; Kosei Yamaguchi; Tetsuaki Fujimoto; Junshi Hotate; Takashi Kishimoto; Toshiki Higashi; Takashi Imagawa; Ryutaro Doi; Munehiro Tada; Tadahiko Sugibayashi; Wataru Takahashi 002; Kazutoshi Wakabayashi; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Fault Diagnosis of Via-Switch Crossbar in Non-volatile FPGA. - Ryutaro Doi; Xu Bai; Toshitsugu Sakamoto; Masanori Hashimoto (DATE, 2020)

33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. - Masanori Hashimoto; Xu Bai; Naoki Banno; Munehiro Tada; Toshitsugu Sakamoto; Jaehoon Yu; Ryutaro Doi; Yusuke Araki; Hidetoshi Onodera; Takashi Imagawa; Hiroyuki Ochi; Kazutoshi Wakabayashi; et al. (ISSCC, 2020)

A Fault Detection and Diagnosis Method for Via-Switch Crossbar in Non-Volatile FPGA. - Ryutaro Doi; Xu Bai; Toshitsugu Sakamoto; Masanori Hashimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020)

Sneak Path Free Reconfiguration With Minimized Programming Steps for Via-Switch Crossbar-Based FPGA. - Ryutaro Doi; Jaehoon Yu; Masanori Hashimoto (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)