A BiCMOS PLL-based data separator circuit with high stability and accuracy. - Shyoichi Miyazawa; Ryutaro Horita; Kenichi Hase; Kazuo Kato; Shinichi Kojima (IEEE J. Solid State Circuits, 1991)

A 240-Mbps, 1-W CMOS EPRML read-channel LSI chip using an interleaved subranging pipeline A/D converter. - Tatsuji Matsuura; Takashi Nara; Tatsuya Komatsu; Eiki Imaizumi; Toshihiro Matsutsuru; Ryutaro Horita; Haruto Katsu; Shintaro Suzumura; Kazuo Sato (IEEE J. Solid State Circuits, 1998)