Implementation of a new neurochip using stochastic logic. - Shigeo Sato; Ken Nemoto; S. Akimoto; Mitsunaga Kinjo; Koji Nakajima (IEEE Trans. Neural Networks, 2003)

Power efficient realtime super resolution by virtual pipeline technique on a server with manycore coprocessors. - Kazuhisa Ishizaka; Takamichi Miyamoto; S. Akimoto; A. Iketani; T. Hosomi; Junji Sakai (COOL Chips, 2013)