A Novel Low Power 1 GS/s S&H Architecture With Improved Analog Bandwidth. - Arashk Norouzpour-Shirazi; S. Arash Mirhaj; Shahin Jafarabadi-Ashtiani; Omid Shoaei (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Linearity improvement of open-loop NMOS source-follower sample and hold circuits. - Arashk Norouzpour-Shirazi; S. Arash Mirhaj; Shahin Jafarabadi-Ashtiani; Omid Shoaei (IET Circuits Devices Syst., 2011)

High speed sample and hold design using closed-loop pole-zero cancelation. - S. Arash Mirhaj; Arashk Norouzpour-Shirazi; Shahin Jafarabadi-Ashtiani; Omid Shoaei (Microelectron. J., 2011)

14.9 Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB. - Zuow-Zun Chen; Yen-Hsiang Wang; Jaewook Shin; Yan Zhao 002; Seyed Arash Mirhaj; Yen-Cheng Kuan; Huan-Neng Ron Chen; Chewnpu Jou; Ming-Hsien Tsai 002; Fu-Lung Hsueh; Mau-Chung Frank Chang (ISSCC, 2015)

Automated Design of Analog Circuits Using Reinforcement Learning. - Keertana Settaluri; Zhaokai Liu; Rishubh Khurana; Arash Mirhaj; Rajeev Jain; Borivoje Nikolic (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)