Fabrication Process for Josephson Integrated Circuits. - J. H. Greiner; Charles J. Kircher; S. P. Klepner; S. K. Lahiri; A. J. Warnecke; S. Basavaiah; E. T. Yen; John M. Baker; P. R. Brosious; H.-C. W. Huang; M. Murakami; Irving Ames (IBM J. Res. Dev., 1980)

Designing a Testable System on a Chip. - Stephen V. Kosonocky; Arthur A. Bright; Kevin W. Warren; Ruud A. Haring; Steve Klepner; Sameh W. Asaad; S. Basavaiah; Bob Havreluk; David F. Heidel; Michael Immediato; Keith A. Jenkins; Rajiv V. Joshi; et al. (VTS, 1998)