Optimization of HfSiON using a design of experiment (DOE) approach on 0.45 V Vt Ni-FUSI CMOS transistors. - A. Rothschild; R. Mitsuhashi; Christoph Kerner; X. Shi; J. L. Everaert; L. Date; Thierry Conard; Olivier Richard; C. Vrancken; R. Verbeeck; Anabela Veloso; A. Lauwers; et al. (Microelectron. Reliab., 2007)

Migrating from planar to FinFET for further CMOS scaling: SOI or bulk? - Thomas Chiarella; Liesbeth Witters; Abdelkarim Mercha; Christoph Kerner; Rok Dittrich; Michal Rakowski; Claude Ortolland; Lars-Åke Ragnarsson; Bertrand Parvais; An De Keersgieter; Stefan Kubicek; Augusto Redolfi; et al. (ESSCIRC, 2009)

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning. - Hans Mertens; M. Hosseini; Thomas Chiarella; D. Zhou; S. Wang; G. Mannaert; E. Dupuy; D. Radisic; Z. Tao; Yusuke Oniki; Andriy Hikavyy; R. Rosseel; et al. (VLSI Technology and Circuits, 2023)

Integration of a Stacked Contact MOL for Monolithic CFET. - Victor Vega-Gonzalez; D. Radisic; Bt Chan; S. Choudhury; S. Wang; A. Mingardi; Q. Toan Le; H. Decoster; Yusuke Oniki; P. Puttarame; Kevin Vandersmissen; J. P. Soulie; et al. (VLSI Technology and Circuits, 2023)

Vt Fine-Tuning in Multi-Vt Gate-All-Around Nanosheet nFETs Using Rare-Earth Oxide-Based Dipole-First Gate Stack Compatible with CFET Integration. - Hiroaki Arimura; Hans Mertens; Jacopo Franco; L. Lukose; W. Maqsood; S. Brus; Thomas Chiarella; A. Impagnatiello; S. Homkar; V. K. Mootheri; C. Yin; G. Alessio Verni; et al. (VLSI Technology and Circuits, 2024)

Monolithic Complementary Field Effect Transistors (CFET) Demonstrated using Middle Dielectric Isolation and Stacked Contacts. - Steven Demuynck; Victor Vega-Gonzalez; C. Toledo de Carvalho Cavalcante; L. Petersen Barbosa Lima; K. Stiers; C. Sheng; A. Vandooren; M. Hosseini; X. Zhou; Hans Mertens; Thomas Chiarella; Jürgen Bömmels; et al. (VLSI Technology and Circuits, 2024)