A second generation Silicon compiler for bit-serial signal processing architecture. - Y. S. Cheung; S. C. Leung (ICASSP, 1987)

Synthesis of Delay-Insensitive Circuits by Refinements into Atomic Threads. - Hon Fung Li; S. C. Leung; P. N. Lam (ICCD, 1991)

An efficient algorithm for the realizability analysis of signal transition graphs. - Hon Fung Li; S. C. Leung (Great Lakes Symposium on VLSI, 1994)

Optimization of state encoding in distributed circuits. - P. N. Lam; Hon Fung Li; S. C. Leung (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

A syntax-directed translation for the synthesis of delay-insensitive circuits. - S. C. Leung; Hon Fung Li (IEEE Trans. Very Large Scale Integr. Syst., 1994)

Sharing Buffer in an Input-Output Buffered ATM Switch without Scaling up Memory Bandwidth Requirement. - Derek Chi-Wai Pao; S. C. Leung (ICCCN, 1995)

On the realizability and synthesis of delay-insensitive behaviors. - S. C. Leung; Hon Fung Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Space division approach to implement a shared buffer in an ATM switch. - Derek Chi-Wai Pao; S. C. Leung (Comput. Commun., 1997)