Circuit activity based logic synthesis for low power reliable operations. - Kaushik Roy 001; S. C. Prasad (IEEE Trans. Very Large Scale Integr. Syst., 1993)

A System for Incremental Synthesis to Gate-Level and Reoptimization Following RTL Design Changes. - S. C. Prasad; P. Anirudhan; Patrick W. Bosshart (DAC, 1994)

Circuit optimization for minimisation of power consumption under delay constraint. - S. C. Prasad; Kaushik Roy 001 (VLSI Design, 1995)

Transistor reordering for power minimization under delay constraint. - S. C. Prasad; Kaushik Roy 001 (ACM Trans. Design Autom. Electr. Syst., 1996)