"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session). - Rajiv V. Joshi; Wei Hwang; S. C. Wilson; Ching-Te Chuang (ISLPED, 2000)

A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology. - Rajiv V. Joshi; Wei Hwang; S. C. Wilson; Ghavam V. Shahidi; Ching-Te Chuang (VLSI Design, 2000)

Improved Monte Carlo Variance Reduction for Space and Energy Self-Shielding. - S. C. Wilson; Rachel N. Slaybaugh (CoRR, 2015)