A Context-Switch Reduction Heuristic for Power-Aware Off-Line Scheduling. - Biju K. Raveendran; Sundar Balasubramaniam; K. Durga Prasad; S. Gurunarayanan 001 (Asia-Pacific Computer Systems Architecture Conference, 2006)

Variants of Priority Scheduling Algorithms for Reducing Context-Switches in Real-Time Systems. - Biju K. Raveendran; K. Durga Prasad; Sundar Balasubramaniam; S. Gurunarayanan 001 (ICDCN, 2006)

EFFS: Efficient Flash File System for Wireless Sensor Nodes. - Biju K. Raveendran; Janardan Prasad Misra; Karan Bhatnagar; S. Gurunarayanan 001 (ESA, 2007)

An Energy Efficient Selective Placement Scheme for Set-Associative Data Cache in Embedded System. - Biju K. Raveendran; T. S. B. Sudarshan; Avinash Patil; Komal B. Randive; S. Gurunarayanan 001 (ESA, 2007)

Evaluation of priority based real time scheduling algorithms: choices and tradeoffs. - Biju K. Raveendran; Sundar Balasubramaniam; S. Gurunarayanan 001 (SAC, 2008)

An efficient method to compute static single assignment form for multicore architecture. - D. C. Kiran; S. Gurunarayanan 001; Janardan Prasad Misra; Faizan Khaliq (RAIT, 2012)

Fine grain thread scheduling on multicore processors: cores with multiple functional units. - Munish Bhatia; D. C. Kiran; Janardan Prasad Misra; S. Gurunarayanan 001 (COMPUTE, 2013)

Architectures and algorithms for image and video processing using FPGA-based platform. - Jai Gopal Pandey; Arindam Karmakar; S. Gurunarayanan 001 (VDAT, 2014)

A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding Algorithm. - Jai Gopal Pandey; Arindam Karmakar; Chandra Shekhar 001; S. Gurunarayanan 001 (VLSID, 2014)

An embedded framework for accurate object localization using center of gravity measure with mean shift procedure. - Jai Gopal Pandey; Arindam Karmakar; Chandra Shekhar 001; S. Gurunarayanan 001 (VDAT, 2015)

An FPGA-Based Architecture for Local Similarity Measure for Image/Video Processing Applications. - Jai Gopal Pandey; Arindam Karmakar; Chandra Shekhar 001; S. Gurunarayanan 001 (VLSID, 2015)

An efficient adaptive block pinning for multicore architectures. - Nitin Chaturvedi; S. Gurunarayanan 001 (Microprocess. Microsystems, 2015)

Global Scheduling Heuristics for Multicore Architecture. - D. C. Kiran; S. Gurunarayanan 001; Janardan Prasad Misra; Abhijeet Nawal (Sci. Program., 2015)

An adaptive migration-replication scheme (AMR) for shared cache in chip multiprocessors. - Nitin Chaturvedi; Arun Subramaniyan 001; S. Gurunarayanan 001 (J. Supercomput., 2015)

Register allocation for fine grain threads on multicore processor. - D. C. Kiran; S. Gurunarayanan 001; Janardan Prasad Misra; Munish Bhatia (J. King Saud Univ. Comput. Inf. Sci., 2017)

A low power high speed MTJ based non-volatile SRAM cell for energy harvesting based IoT applications. - Kanika; R. Sankara Prasad; Nitin Chaturvedi; S. Gurunarayanan 001 (Integr., 2019)

A testbed validated simple time synchronization protocol for clustered wireless sensor networks for IoT. - G. Sai Sesha Chalapathi; Vinay Chamola; S. Gurunarayanan 001 (J. Intell. Fuzzy Syst., 2019)

Integrated Cooperative Synchronization for Wireless Sensor Networks. - G. Sai Sesha Chalapathi; Bernhard Etzlinger; S. Gurunarayanan 001; Andreas Springer (IEEE Wirel. Commun. Lett., 2019)

Twin-Coupled Sense Amplifier to improve margin in 1T-1MTJ based MRAM array. - Kanika Monga; Lakshaya Maheshwari; Nitin Chaturvedi; S. Gurunarayanan 001 (VDAT, 2020)

An optimal delay aware task assignment scheme for wireless SDN networked edge cloudlets. - G. Sai Sesha Chalapathi; Vinay Chamola; Chen-Khong Tham; S. Gurunarayanan 001; Nirwan Ansari (Future Gener. Comput. Syst., 2020)

Design of an MTJ/CMOS-Based Asynchronous System for Ultra-Low Power Energy Autonomous Applications. - Kanika Monga; Kunal Harbhajanka; Arush Srivastava; Nitin Chaturvedi; S. Gurunarayanan 001 (J. Circuits Syst. Comput., 2021)

Design of a Programmable Delay Line with On-Chip Calibration to Achieve Immunity Against Process Variations. - Kanika Monga; Eesha Karnawat; Nitin Chaturvedi; S. Gurunarayanan 001 (VDAT, 2022)

Energy Efficient Ternary Multi-trit Multiplier Design Using Novel Adders. - Aalelai Vendhan; Syed Ershad Ahmed; S. Gurunarayanan 001 (Circuits Syst. Signal Process., 2024)

Tunable Energy-Efficient Approximate Circuits for Self-Powered AI and Autonomous Edge Computing Systems. - Shubham Garg; Kanika Monga; Nitin Chaturvedi; S. Gurunarayanan 001 (IEEE Access, 2025)

Design of Approximate Adder With Reconfigurable Accuracy. - Aalelai Vendhan; Syed Ershad Ahmed; S. Gurunarayanan 001 (IEEE Access, 2025)