No-race charge recycling complementary pass transistor logic (NCRCPL) for low power applications. - Ali Abbasian; S. H. Rasouli; Ali Afzali-Kusha; Mehrdad Nourani (ISCAS (5), 2003)

Double edge triggered Feedback Flip-Flop in sub 100NM technology. - S. H. Rasouli; Amir Amirabadi; A. Seyedi; Ali Afzali-Kusha (ASP-DAC, 2006)

Low power and high performance clock delayed domino logic using saturated keeper. - Amir Amirabadi; A. Chehelcheraghi; S. H. Rasouli; A. Seyedi; Ali Afzali-Kusha (ISCAS, 2006)

Low power low leakage clock gated static pulsed flip-flop. - A. S. Seyedi; S. H. Rasouli; Amir Amirabadi; Ali Afzali-Kusha (ISCAS, 2006)

Clock Gated Static Pulsed Flip-Flop (CGSPFF) in Sub 100 nm Technology. - A. S. Seyedi; S. H. Rasouli; Amir Amirabadi; Ali Afzali-Kusha (ISVLSI, 2006)