3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections. - Katsuyuki Sakuma; Paul S. Andry; Cornelia K. Tsang; Steven L. Wright; Bing Dang; Chirag S. Patel; Bucknell C. Webb; J. Maria; Edmund J. Sprogis; S. K. Kang; Robert J. Polastre; Raymond R. Horton; et al. (IBM J. Res. Dev., 2008)