High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit. - S. Kala; Nalesh Sivanandan; Arka Maity; S. K. Nandy 001; Ranjani Narayan (ISCAS, 2013)

Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM Systems. - S. Kala; Nalesh Sivanandan; S. K. Nandy 001; Ranjani Narayan (ISED, 2014)

Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture. - S. Kala; Nalesh Sivanandan; S. K. Nandy 001; Ranjani Narayan (J. Low Power Electron., 2015)

Two dimensional FFT architecture based on radix-43 algorithm with efficient output reordering. - S. Kala; Nalesh Sivanandan; Babita R. Jose; Jimson Mathew; Marco Ottavi (DTIS, 2018)

Design Space Exploration of Convolution Algorithms to Accelerate CNNs on FPGA. - S. Kala; Debdeep Paul; Babita R. Jose; Nalesh Sivanandan (ISED, 2018)

A Hardware Accelerator for Convolutional Neural Network Using Fast Fourier Transform. - S. Kala; Babita R. Jose; Debdeep Paul; Jimson Mathew (VDAT, 2018)

Efficient Hardware Acceleration of Convolutional Neural Networks. - S. Kala; Babita R. Jose; Jimson Mathew; Nalesh Sivanandan (SoCC, 2019)

UniWiG: Unified Winograd-GEMM Architecture for Accelerating CNN on FPGAs. - S. Kala; Jimson Mathew; Babita R. Jose; Nalesh Sivanandan (VLSID, 2019)

Radix-43 based two-dimensional FFT architecture with efficient data reordering scheme. - S. Kala; Jimson Mathew; Babita R. Jose; Nalesh Sivanandan (IET Comput. Digit. Tech., 2019)

High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture. - S. Kala; Babita R. Jose; Jimson Mathew; Nalesh Sivanandan (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Bandwidth-Efficient Sparse Matrix Multiplier Architecture for Deep Neural Networks on FPGA. - Mahesh M; Nalesh S 001; S. Kala (SoCC, 2021)

Hardware Acceleration of SpMV Multiplier for Deep Learning. - Mahesh Mahadurkar; Nalesh Sivanandan; S. Kala (VDAT, 2021)

Adiabatic Physical Unclonable Function Using Cross-Coupled Pair. - Vishnu Bajjuri; Nalesh S 001; Sree Ranjani Rajendran; S. Kala (iSES, 2022)

Bit-Flip Attack Detection for Secure Sparse Matrix Computations on FPGA. - Noble G; Nalesh S 001; S. Kala (APCCAS, 2023)

Approximate CNN on FPGA Using Toom-Cook Multiplier. - Abhinav Kalvacherla; Rachana George; Nalesh S 001; S. Kala (iSES, 2023)

MOSCON: Modified Outer Product based Sparse Matrix-Matrix Multiplication Accelerator with Configurable Tiles. - Noble G; Nalesh S 001; S. Kala (VLSID, 2023)

A physically unclonable function architecture with multiple responses on FPGA. - M. A. Muneeb; Nalesh S 001; S. Kala (Int. J. Embed. Syst., 2023)

FPGA-Based Acceleration of Homomorphic Convolution with Plaintext Kernels - Extended Abstract. - Rohith George Ninan; S. Kala (SPACE, 2024)

A Novel CNN Architecture for Herb Classification. - Sweety Kunjachan; Anjuru Muni Santhosh; S. Kala (TENCON, 2024)