A C-testable parallel multiplier using differential cascode voltage switch (DDVS) logic. - W. A. J. Waller; S. M. Aziz (VLSI, 1993)

On Testability of Differential Split-Level CMOS Circuits. - S. M. Aziz; W. A. J. Waller (VLSI Design, 1994)

A C-testable modified Booth's array multiplier. - S. M. Aziz (VLSI Design, 1995)

Fault Characterization of Low Capacitance Full-Swing BiCMOS Logic Circuits. - S. M. Aziz; Joarder Kamruzzaman (Asian Test Symposium, 1998)