Reduction of Substrate Noise in Sub Clock Frequency Range. - S. M. Yasser Sherazi; Shahzad Asif; Erik Backenius; Mark Vesterbacka (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Synthesis strategies for sub-VT systems. - Pascal Andreas Meinerzhagen; Oskar Andersson; S. M. Yasser Sherazi; Andreas Peter Burg; Joachim Neves Rodrigues (ECCTD, 2011)

Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain. - S. M. Yasser Sherazi; Peter Nilsson 001; Omer Can Akgun; Henrik Sjöland; Joachim Neves Rodrigues (ISCAS, 2011)

Impact of switching activity on the energy minimum voltage for 65 nm sub-VT CMOS. - Oskar Andersson; S. M. Yasser Sherazi; Joachim Neves Rodrigues (NORCHIP, 2011)

Benchmarking of Standard-Cell Based Memories in the Sub- VT Domain in 65-nm CMOS Technology. - Pascal Andreas Meinerzhagen; S. M. Yasser Sherazi; Andreas Peter Burg; Joachim Neves Rodrigues (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS. - Pascal Andreas Meinerzhagen; Oskar Andersson; Babak Mohammadi; S. M. Yasser Sherazi; Andreas Peter Burg; Joachim Neves Rodrigues (ESSCIRC, 2012)

A 100-fJ/cycle sub-VT decimation filter chain in 65 nm CMOS. - S. M. Yasser Sherazi; Peter Nilsson 001; Henrik Sjöland; Joachim Neves Rodrigues (ICECS, 2012)

A Receiver Architecture for Devices in Wireless Body Area Networks. - Henrik Sjöland; John B. Anderson; Carl Bryant; Rohit Chandra; Ove Edfors; Anders J. Johansson; Nafiseh Seyed Mazloum; Reza Meraji; Peter Nilsson 001; Dejan Radjen; Joachim Neves Rodrigues; S. M. Yasser Sherazi; et al. (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

Power savings in digital filters for wireless communication. - Peter Nilsson 001; Anusha Gundarapu; S. M. Yasser Sherazi (ECCTD, 2013)

Analog and digital approaches for an energy efficient low complexity channel decoder. - Reza Meraji; S. M. Yasser Sherazi; John B. Anderson; Henrik Sjöland; Viktor Öwall (ISCAS, 2013)

Ultra low energy design exploration of digital decimation filters in 65 nm dual-VT CMOS in the sub-VT domain. - S. M. Yasser Sherazi; Joachim Neves Rodrigues; Omer Can Akgun; Henrik Sjöland; Peter Nilsson 001 (Microprocess. Microsystems, 2013)

Supply-voltage down conversion for digital CMOS designs. - Peter Nilsson 001; Mohammed Azher Ali; Manivannan Ethiraj; S. M. Yasser Sherazi (ICECS, 2014)

A digital baseband for low power FSK based receiver in 65 nm CMOS. - S. M. Yasser Sherazi; Henrik Sjöland; Peter Nilsson 001 (ICECS, 2014)

Ultra low power transceivers for wireless sensors and body area networks. - Henrik Sjöland; John B. Anderson; Carl Bryant; Rohit Chandra; Ove Edfors; Anders J. Johansson; Nafiseh Seyed Mazloum; Reza Meraji; Peter Nilsson 001; Dejan Radjen; Joachim Neves Rodrigues; S. M. Yasser Sherazi; et al. (ISMICT, 2014)

Low Power Analog and Digital (7, 5) Convolutional Decoders in 65 nm CMOS. - Reza Meraji; S. M. Yasser Sherazi; John B. Anderson; Henrik Sjöland; Viktor Öwall (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)