Design of DADDA Multiplier Using High Performance and Low Power Full Adder. - S. Nagaleela; G. Shanthi; Boppa Manisha; Palle Bharath; Erram Praneeth (ICCCNT, 2023)

VLSI Design of High Performance FIR Filter using High Speed Hybrid Multiplier. - S. Nagaleela; Kasireddy Swetha; Dorsela Keerthi Chandrika; Dhanush Goud Kalali; G. Shanthi (ICCCNT, 2024)

Design of Shift Registers Using DG-FinFET for Low Power Applications. - G. Shanthi; K. Naga Vaishnavi; N. Manasa; V. Surya Pramod; S. Naga Leela; Shaik Shoukath Vali (ICDCS, 2024)