An efficient embedded multi-ported memory architecture for next-generation FPGAs. - S. Navid Shahrouzi; Darshika G. Perera (ASAP, 2017)

An efficient FPGA-based memory architecture for compute-intensive applications on embedded devices. - S. Navid Shahrouzi; Darshika G. Perera (PACRIM, 2017)

Dynamic partial reconfigurable hardware architecture for principal component analysis on mobile and embedded devices. - S. Navid Shahrouzi; Darshika G. Perera (EURASIP J. Embed. Syst., 2017)

Optimized Counter-Based Multi-Ported Memory Architectures for Next-Generation FPGAs. - S. Navid Shahrouzi; Darshika G. Perera (SoCC, 2018)

HDL Code Optimizations: Impact on Hardware Implementations and CAD Tools. - S. Navid Shahrouzi; Darshika G. Perera (PACRIM, 2019)

Optimized hardware accelerators for data mining applications on embedded platforms: Case study principal component analysis. - S. Navid Shahrouzi; Darshika G. Perera (Microprocess. Microsystems, 2019)

Towards Composing Optimized Bi-Directional Multi-Ported Memories for Next-Generation FPGAs. - S. Navid Shahrouzi; Arkan Alkamil; Darshika G. Perera (IEEE Access, 2020)

Composing Efficient Computational Models for Real-Time Processing on Next-Generation Edge-Computing Platforms. - Mokhles A. Mohsin; S. Navid Shahrouzi; Darshika G. Perera (IEEE Access, 2024)