Design of Neural Network on FPGA. - S. P. Joy Vasantha Rani; P. Kanagasabapathy (ESA/VLSI, 2004)

Field Programmable Gate Array based floating point hardware design of recursive k-means clustering algorithm for Radial Basis Function Neural Network. - S. P. Joy Vasantha Rani; P. Kanagasabapathy; L. Suganthi (Int. J. Intell. Syst. Technol. Appl., 2009)

Reconfigurable RNS FIR Filter Using Higher Radix Multiplier. - J. Britto Pari; S. P. Joy Vasantha Rani (ACITY (3), 2012)

Pipelined hardware design of self tuning controller with on-chip parameter estimator. - S. P. Joy Vasantha Rani (Int. J. High Perform. Syst. Archit., 2015)

An ADC BIST using on-chip ramp generation and digital ORA. - Senthil Sivakumar; S. P. Joy Vasantha Rani (Microelectron. J., 2018)

Automatic fault isolation and restoration of distribution system using JADE based Multi-Agents. - Indhumathi Chellaswamy; S. P. Joy Vasantha Rani (Turkish J. Electr. Eng. Comput. Sci., 2019)

Efficient Design of ADC BIST with an Analog Ramp Signal Generation and Digital Error Estimation. - Senthil Sivakumar; S. P. Joy Vasantha Rani (J. Circuits Syst. Comput., 2019)

Performance analysis of intrinsic embedded evolvable hardware using memetic and genetic algorithms. - Ranjith Chandrasekharan; S. P. Joy Vasantha Rani (Int. J. Bio Inspired Comput., 2020)

A Fast On-Chip Adaptive Genetic Algorithm Processor for Evolutionary FIR Filter Implementation Using Hardware-Software Co-Design. - Chandran Ranjith; S. P. Joy Vasantha Rani (J. Circuits Syst. Comput., 2020)

Nonlinear Controller: Voltage Controlled PFC-Based Fuzzy MDPSM Controller with Predictive Input Voltage. - R. Thangam; S. P. Joy Vasantha Rani (J. Circuits Syst. Comput., 2020)

Wire-Length and Run-Time Optimization in FPGA Placement Using Hybrid Iterative Algorithms. - P. Sudhanya; S. P. Joy Vasantha Rani (J. Circuits Syst. Comput., 2021)

Realization of Deep Learning Based Embedded Soft Sensor for Bioprocess Application. - V. V. S. Vijaya Krishna; N. Pappa; S. P. Joy Vasantha Rani (Intell. Autom. Soft Comput., 2022)

Approximate Multipliers Design Using Approximate Adders for Image Processing Applications. - S. P. Joy Vasantha Rani; J. R. Lourdu Jennifer; P. Sudhanya (J. Circuits Syst. Comput., 2022)

Analysis of FPGA Architecture with Hybrid Logic Blocks Based on ULG and LUT. - P. Sudhanya; S. P. Joy Vasantha Rani (J. Circuits Syst. Comput., 2025)