Rewrite Systems for Protocol Specification and Verification. - S. Ramanathan; G. Sivakumar (FORTE, 1990)

A Methodology for Generating Application Specific Tree Multipliers. - S. Ramanathan; Nibedita Mohanty; V. Visvanathan (VLSI Design, 1993)

An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters. - V. Visvanathan; Nibedita Mohanty; S. Ramanathan (VLSI Design, 1993)

A modular systolic architecture for delayed least mean squares adaptive filtering. - V. Visvanathan; S. Ramanathan (VLSI Design, 1995)

A systolic architecture for LMS adaptive filtering with minimal adaptation delay. - S. Ramanathan; V. Visvanathan (VLSI Design, 1996)

Low-Power Configurable Processor Array for DLMS Adaptive Filtering. - S. Ramanathan; V. Visvanathan (VLSI Design, 1997)

Synthesis of Configurable Architectures for DSP Algorithms. - S. Ramanathan; V. Visvanathan; S. K. Nandy 001 (VLSI Design, 1999)

Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay1. - S. Ramanathan; V. Visvanathan (Integr., 1999)

Synthesis of ASIPs for DSP algorithms. - S. Ramanathan; V. Visvanathan; S. K. Nandy 001 (Integr., 1999)

A computational engine for multirate FIR digital filtering. - S. Ramanathan; V. Visvanathan; S. K. Nandy 001 (Signal Process., 1999)

Architectural Synthesis of Computational Engines for Subband Adaptive Filtering. - S. Ramanathan; V. Visvanathan; S. K. Nandy 001 (J. VLSI Signal Process., 1999)

Reconfigurable Filter Coprocessor Architecture for DSP Applications. - S. Ramanathan; S. K. Nandy 001; V. Visvanathan (J. VLSI Signal Process., 2000)

Need aspect approval system for procurement of components used for INDIAN satellite program. - Jagadamaba Prasad Singh; S. M. Kattimani; Rakesh Kumar; S. Ramanathan; G. N. V. Prasad (RAIT, 2018)

Building a Smarter Shield: Using Ensemble Learning for Multi-Class DDoS Attacks. - M. Vijayalakshmi; A Susmanth Srinivas; S. Ramanathan (ICCCNT, 2024)