Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability. - F. Duan; R. Castagnetti; R. Venkatraman; O. Kobozeva; S. Ramesh 004 (ISQED, 2003)

A High-Performance SRAM Technology With Reduced Chip-Level Routing Congestion for SoC. - Ruggero Castagnetti; R. Venkatraman; Brandon Bartz; Carl Monzel; T. Briscoe; Andres Teene; S. Ramesh 004 (ISQED, 2005)

Impact of Interconnect Process Variations on Memory Performance and Design. - Andres Teene; Bob Davis; Ruggero Castagnetti; Jeff Brown; S. Ramesh 004 (ISQED, 2005)

The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability. - R. Venkatraman; R. Castagnetti; S. Ramesh 004 (ISQED, 2006)

Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design. - R. Venkatraman; R. Castagnetti; Andres Teene; Benjamin Mbouombouo; S. Ramesh 004 (ISQED, 2009)