High speed modular systolic array-based DTCWT with parallel processing architecture for 2D image transformation on FPGA. - S. S. Divakara; Sudarshan Patilkulkarni; Cyril Prasanna Raj (Int. J. Wavelets Multiresolution Inf. Process., 2017)

High Speed Area Optimized Hybrid DA Architecture for 2D-DTCWT. - S. S. Divakara; Sudarshan Patilkulkarni; Cyril Prasanna Raj (Int. J. Image Graph., 2018)

Novel DWT/IDWT Architecture for 3D with Nine Stage 2D Parallel Processing using Split Distributed Arithmetic. - S. S. Divakara; Sudarshan Patilkulkarni; Cyril Prasanna Raj (Int. J. Image Graph., 2020)