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Bottom-up methodology for predictive simulations of self-heating in aggressively scaled process technologies. - D. Singh; Oscar D. Restrepo; P. P. Manik; N. Rao Mavilla; H. Zhang; Peter C. Paliwoda; S. Pinkett; Y. Deng; Eduardo Cruz Silva; Jeffrey B. Johnson; M. Bajaj; S. Furkay; et al. (IRPS, 2018)

High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories. - Romain Ritzenthaler; Elena Capogreco; E. Dupuy; Hiroaki Arimura; J. P. Bastos; P. Favia; F. Sebaai; D. Radisic; V. T. H. Nguyen; G. Mannaert; B. T. Chan; V. Machkaoutsan; et al. (VLSI Technology and Circuits, 2022)

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning. - Hans Mertens; M. Hosseini; Thomas Chiarella; D. Zhou; S. Wang; G. Mannaert; E. Dupuy; D. Radisic; Z. Tao; Yusuke Oniki; Andriy Hikavyy; R. Rosseel; et al. (VLSI Technology and Circuits, 2023)