Design and analysis of a hybrid encoded low power multiplier with reduced transition activity technique. - S. Saravanan 004; M. Madheswaran (ICWET, 2010)

Design and Analysis of a Spurious Switching Suppression Technique Equipped Low Power Multiplier with Hybrid Encoding Scheme - S. Saravanan 004; M. Madheswaran (CoRR, 2010)