Survey on Efficient, Low-power, AES Image Encryption and Bio-cryptography Schemes. - S. Sridevi Sathya Priya; P. Karthigaikumar; N. M. Siva Mangai; P. T. Vanathi (Smart Comput. Rev., 2012)

Efficient hardware implementation of AES algorithm using bio metric key. - S. Sridevi Sathya Priya; P. Karthigaikumar; N. M. Siva Mangai; R. Sandhya (Int. J. Inf. Commun. Technol., 2015)

An Efficient Hardware Architecture for High Throughput AES Encryptor Using MUX Based Sub Pipelined S-Box. - S. Sridevi Sathya Priya; P. Karthigaikumar; N. M. Siva Mangai; P. Kirti Gaurav Das (Wirel. Pers. Commun., 2017)

High Throughput AES Algorithm Using Parallel Subbytes and MixColumn. - S. Sridevi Sathya Priya; P. Karthigaikumar; N. M. Siva Mangai; V. Rejula (Wirel. Pers. Commun., 2017)

Design and Evaluation of XOR Arbiter Physical Unclonable Function and its Implementation on FPGA in Hardware Security Applications. - Naveenkumar R; N. M. Sivamangai; Napolean A; S. Sridevi Sathya Priya (J. Electron. Test., 2022)

Design of INV/BUFF Logic Locking For Enhancing the Hardware Security. - Naveenkumar R; N. M. Sivamangai; Napolean A; S. Sridevi Sathya Priya; S. V. Ashika (J. Electron. Test., 2023)

Analysis of Various Visual Cryptographic Techniques and their Issues Based on Optimization Algorithms. - A. S. Sajitha; S. Sridevi Sathya Priya (Int. J. Image Graph., 2023)

Implementation of Efficient Security Algorithm. - A. Vinodhini; S. Sridevi Sathya Priya; P. Karthigaikumar; N. M. Siva Mangai (ICDCS, 2024)