S. Srinivasan
Affiliations:- IIT Madras
According to our database1,
S. Srinivasan
authored at least 21 papers
between 1986 and 2011.
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Bibliography
2011
Proceedings of the International Symposium on Electronic System Design, 2011
2010
IEEE Trans. Broadcast., 2010
2007
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
2006
A parallel algorithm, architecture and FPGA realization for landmark determination and map construction in a planar unknown environment.
Parallel Comput., 2006
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
2005
Design and FPGA implementation of an MPEG based video scalar with reduced on-chip memory utilization.
J. Syst. Archit., 2005
2004
A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
2003
A Novel Architecture for Lifting-Based Discrete Wavelet Transform for JPEG2000 Standard suitable for VLSI.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003
Proceedings of the 2003 International Symposium on Information Technology (ITCC 2003), 2003
Reduced Memory Implementation of Modified Serial Watershed Algorithm Based On Ordered Queue.
Proceedings of the 2003 International Symposium on Information Technology (ITCC 2003), 2003
Design and FPGA Implementation of a Video Scalar with on-chip reduced memory utilization.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003
2002
VLSI Design, 2002
A Dynamically Reconfigurable Video Compression Scheme Using FPGAs with Coarse-grain Parallelism.
VLSI Design, 2002
A fast, FPGA-based MPEG-2 video encoder with a novel automatic quality control scheme.
Microprocess. Microsystems, 2002
VLSI Implementation of 2-D DWT/IDWT Cores Using 9/7-Tap Filter Banks Based on the Non-Expansive Symmetric Extension Scheme.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
2001
FPGA implementation of a novel, fast motion estimation algorithm for real-time video compression.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2001
2000
Design and implementation of an EPLD-based variable length coder for real time image compression applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
EPLD-based architecture of real time 2D-discrete cosine transform and quantization for image compression.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
1986
Microprocess. Microsystems, 1986