New design for an 82720-based colour graphics generator. - P. Prabhakar Rao; S. Srinivasan 001 (Microprocess. Microsystems, 1986)

EPLD-based architecture of real time 2D-discrete cosine transform and quantization for image compression. - Seetharaman Ramachandran; S. Srinivasan 001; R. Chen (ISCAS (3), 1999)

Parallel Implementation of 2D-Discrete Cosine Transform Using EPLDs. - D. V. R. Murthy; Seetharaman Ramachandran; S. Srinivasan 001 (VLSI Design, 1999)

A programmable pruning level control based MPEG video encoder. - Seetharaman Ramachandran; S. Srinivasan 001 (ISCAS, 2000)

Design and implementation of an EPLD-based variable length coder for real time image compression applications. - Seetharaman Ramachandran; S. Srinivasan 001 (ISCAS, 2000)

FPGA implementation of a novel, fast motion estimation algorithm for real-time video compression. - Seetharaman Ramachandran; S. Srinivasan 001 (FPGA, 2001)

VLSI Implementation of 2-D DWT/IDWT Cores Using 9/7-Tap Filter Banks Based on the Non-Expansive Symmetric Extension Scheme. - Kavish Seth; S. Srinivasan 001 (ASP-DAC/VLSI Design, 2002)

A fast, FPGA-based MPEG-2 video encoder with a novel automatic quality control scheme. - Seetharaman Ramachandran; S. Srinivasan 001 (Microprocess. Microsystems, 2002)

A Dynamically Reconfigurable Video Compression Scheme Using FPGAs with Coarse-grain Parallelism. - Seetharaman Ramachandran; S. Srinivasan 001 (VLSI Design, 2002)

A Novel, Automatic Quality Control Scheme for Real Time Image Transmission. - Seetharaman Ramachandran; S. Srinivasan 001 (VLSI Design, 2002)

Design and FPGA Implementation of a Video Scalar with on-chip reduced memory utilization. - Seetharaman Ramachandran; S. Srinivasan 001 (DSD, 2003)

Reduced Memory Implementation of Modified Serial Watershed Algorithm Based On Ordered Queue. - Kumud Prakash Gupta; S. Srinivasan 001 (ITCC, 2003)

A Distributed Memory Architecture for Morphological Image Processing. - A. Durga Kishore; S. Srinivasan 001 (ITCC, 2003)

A Novel Architecture for Lifting-Based Discrete Wavelet Transform for JPEG2000 Standard suitable for VLSI. - Srikar Movva; S. Srinivasan 001 (VLSI Design, 2003)

A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation. - Kavish Seth; P. Rangarajan; S. Srinivasan 001; V. Kamakoti 001; V. Bala Kuteshwar (VLSI Design, 2004)

Design and FPGA implementation of an MPEG based video scalar with reduced on-chip memory utilization. - Seetharaman Ramachandran; S. Srinivasan 001 (J. Syst. Archit., 2005)

Ultra Folded High-Speed Architectures for Reed-Solomon Decoders. - Kavish Seth; K. N. Viswajith; S. Srinivasan 001; V. Kamakoti 001 (VLSI Design, 2006)

A parallel algorithm, architecture and FPGA realization for landmark determination and map construction in a planar unknown environment. - P. Rajesh Kumar; K. Sridharan 001; S. Srinivasan 001 (Parallel Comput., 2006)

Rapid Abstract Control Model for Signal Processing Implementation. - Kannan Gaddam; Nitin Chandrachoodan; S. Srinivasan 001 (SiPS, 2007)

Efficient Motion Vector Recovery Algorithm for H.264 Using B-Spline Approximation. - Kavish Seth; V. Kamakoti 001; S. Srinivasan 001 (IEEE Trans. Broadcast., 2010)

Towards Quick Solutions for Generalized Placement Problem. - S. Srinivasan 001; V. Kamakoti 001; A. Bhattacharya (ISED, 2011)